Journal: IEEE Trans. on Circuits and Systems

Volume 51-II, Issue 5

213 -- 216George I. Bourdopoulos. Adaptive order reduction scheme for high-order single-bit ΔΣ Modulators
217 -- 221Ragnarok Pak-Kee Chan, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pang Pun. A low-latency asynchronous shift register
222 -- 227Guillermo Fernández-Anaya, J. C. Martínez-García, Vladimír Kucera, D. Aguilar-George. MIMO systems properties preservation under SPR substitutions
228 -- 233Xianlong Hong, Sheqin Dong, Gang Huang, Yici Cai, Chung-Kuan Cheng, Jun Gu. Corner block list representation and its application to floorplan optimization
234 -- 240Wenjie J. Hu, Qing Song. An accelerated decomposition algorithm for robust support vector Machines
241 -- 248Volkan Kursun, Siva G. Narendra, Vivek K. De, Eby G. Friedman. Low-voltage-swing monolithic dc-dc conversion
249 -- 253Rosario Mita, Gaetano Palumbo, Salvatore Pennisi. Effect of CFOA nonidealities in Miller integrator cells
254 -- 256Kong-Pang Pun, Chiu-sing Choy, Cheong-fat Chan, José Epifânio da Franca. An I/Q mismatch-free switched-capacitor complex sigma-delta Modulator
257 -- 261Jaime Ramírez-Angulo, Ramón González Carvajal, Gladys Omayra Ducoudray, Antonio J. López-Martín, Antonio Torralba 0002. New compact CMOS continuous-time low-Voltage analog rank-order filter architecture
262 -- 268Zidong Wang, James Lam, Xiaohui Liu. Exponential filtering for uncertain Markovian jump time-delay systems with nonlinear disturbances
269 -- 275Sang-Min Yoo, Jong-Bum Park, Seung-Hoon Lee, Un-Ku Moon. A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching