| 317 | -- | 318 | Vladimir Stojanovic, Chih-Kong Ken Yang, Ron Ho. Guest Editorial for Special Issue on High-Performance Multichip Interconnections |
| 319 | -- | 323 | Shih-Yuan Kao, Shen-Iuan Liu. A 20-Gb/s Transmitter With Adaptive Preemphasis in 65-nm CMOS Technology |
| 324 | -- | 328 | Kuo-Hsing Cheng, Yu-Chang Tsai, Yen-Hsueh Wu, Ying-Fu Lin. A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications |
| 329 | -- | 333 | Ahmed Nassar, Ahmed Emira, Ahmed Nader Mohieldin, Ahmed Hussien Khalil. Multichannel Clock and Data Recovery: A Synchronous Approach |
| 334 | -- | 338 | Jaejun Lee, Sungho Lee, Sangwook Nam. Multi-Slot Main Memory System for Post DDR3 |
| 339 | -- | 342 | Farshid Aryanfar, Amir Amirkhany. A Low-Cost Resonance Mitigation Technique for Multidrop Memory Interfaces |
| 343 | -- | 347 | Arun Palaniappan, Samuel Palermo. Power Efficiency Comparisons of Interchip Optical Interconnect Architectures |
| 348 | -- | 352 | Jung-Won Han, Boo-Young Choi, Mikyung Seo, Jisook Yun, Dongmyung Lee, Taewook Kim, YunSeong Eo, Sung Min Park. A 20-Gb/s Transformer-Based Current-Mode Optical Receiver in 0.13-μm CMOS |
| 353 | -- | 358 | Won Namgoong, Lei Feng. Digital Processing of Single-Carrier Cyclic Prefixed Frequency Channelized Receiver for Serial Links |
| 359 | -- | 363 | Rajan Narasimha, Naresh R. Shanbhag. Design of Energy-Efficient High-Speed Links via Forward Error Correction |
| 364 | -- | 368 | Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli. Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands |
| 369 | -- | 373 | Meng-Hung Shen, Jen-Huan Tsai, Po-Chiun Huang. Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC |
| 374 | -- | 378 | Lucas Andrew Milner, Gabriel A. Rincón-Mora. A Feedforward 10times CMOS Current-Ripple Suppressor for Switching Power Supplies |
| 379 | -- | 383 | Young Hun Seo, Young Sang Kim, Hong June Park, Jae-Yoon Sim. A 5 Gb/s Transmitter With a TDR-Based Self-Calibration of Preemphasis Strength |
| 384 | -- | 388 | Qiang Zhu, Yang Xu. Quadrature Sampling for Built-In Analog/RF IC Spectrum Test |
| 389 | -- | 393 | Karun Rawat, Meenakshi Rawat, Fadhel M. Ghannouchi. Compensating I-Q Imperfections in Hybrid RF/Digital Predistortion With an Adapted Lookup Table Implemented in an FPGA |
| 394 | -- | 398 | Roger Yubtzuan Chen, Zong-Yi Yang. Modeling the High-Frequency Degradation of Phase/Frequency Detectors |
| 399 | -- | 403 | Bo Fu, Paul Ampadu. Exploiting Parity Computation Latency for On-Chip Crosstalk Reduction |