| 497 | -- | 501 | Jeffrey S. Walling, David J. Allstot. Linearizing CMOS Switching Power Amplifiers Using Supply Regulators |
| 502 | -- | 506 | Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, Jong-Kee Kwon. A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique |
| 507 | -- | 511 | Tejinder Singh Sandhu, Kamal El-Sankary, Ezz I. El-Masry. A Distortion-Compensated Charge Transfer Amplifier for a 1.66-MHz Cyclic Pipeline ADC |
| 512 | -- | 516 | Heather Orser, Anand Gopinath. A 20 GS/s 1.2 V 0.13 muhboxm CMOS Switched Cascode Track-and-Hold Amplifier |
| 517 | -- | 521 | Min C. Park, Michael H. Perrott, Robert Bogdan Staszewski. A Time-Domain Resolution Improvement of an RF-DAC |
| 522 | -- | 526 | Chin-Lung Yang, Shin-Yi Shu, Yi-Chyun Chiang. Design of a K-Band Chip Filter With Three Tunable Transmission Zeros Using a Standard 0.13-muhboxm CMOS Technology |
| 527 | -- | 530 | Toru Tanzawa. A Behavior Model of a Dickson Charge Pump Circuit for Designing a Multiple Charge Pump System Distributed in LSIs |
| 531 | -- | 535 | Alex K. Y. Wong, Ka Nang Leung, Kong-Pang Pun, Yuan-Ting Zhang. A 0.5-Hz High-Pass Cutoff Dual-Loop Transimpedance Amplifier for Wearable NIR Sensing Device |
| 536 | -- | 540 | Chih-Jung Chen, Tah-Hsiung Chu, Chih-Lung Lin, Zeui-Chown Jou. A Study of Loosely Coupled Coils for Wireless Power Transfer |
| 541 | -- | 545 | Rajeev K. Dokania, Xiao Wang, Siddharth G. Tallur, Carlos I. Dorta-Quinones, Alyssa B. Apsel. An Ultralow-Power Dual-Band UWB Impulse Radio |
| 546 | -- | 550 | Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee. A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators |
| 551 | -- | 555 | Honggang Qi, Qingming Huang, Wen Gao. A Low-Cost Very Large Scale Integration Architecture for Multistandard Inverse Transform |
| 556 | -- | 560 | Won Namgoong. Flicker Noise in Observer-Controller Digital PLL |
| 561 | -- | 565 | Hyunbean Yi, Sandip Kundu, Sangwook Cho, Sungju Park. A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains |
| 566 | -- | 570 | Cheng-Chi Wong, Hsie-Chia Chang. Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System |
| 571 | -- | 575 | Sheau-Fang Lei, Shin-Chi Lai, Po-Yin Cheng, Ching-Hsing Luo. Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms |