| 797 | -- | 821 | Aiqun Cao, Ruibing Lu, Chen Li 0004, Cheng-Kok Koh. Postlayout optimization for synthesis of Domino circuits |
| 822 | -- | 847 | André C. Nácul, Tony Givargis. Synthesis of time-constrained multitasking embedded software |
| 848 | -- | 879 | Kunhyuk Kang, Bipul C. Paul, Kaushik Roy. Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters |
| 880 | -- | 889 | Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu. Decomposition of instruction decoders for low-power designs |
| 890 | -- | 915 | Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang. Crosstalk minimization in logic synthesis for PLAs |
| 916 | -- | 938 | Sezer Gören, F. Joel Ferguson. Test sequence generation for controller verification and test with high coverage |
| 939 | -- | 952 | Zhong-Zhen Wu, Shih-Chieh Chang. Multiple wire reconnections based on implication flow graph |
| 953 | -- | 973 | Chi-Shong Wang, Chingwei Yeh. Performance-driven technology mapping with MSG partition and selective gate duplication |