| 1 | -- | 2 | Nikil D. Dutt. Editorial |
| 3 | -- | 25 | Tony Givargis. Zero cost indexing for improved processor cache performance |
| 26 | -- | 43 | George A. Constantinides. Word-length optimization for differentiable nonlinear systems |
| 44 | -- | 51 | Qing Su, Jamil Kawa, Charles Chiang, Yehia Massoud. Accurate modeling of substrate resistive coupling for floating substrates |
| 52 | -- | 69 | Azadeh Davoodi, Ankur Srivastava. Effective techniques for the generalized low-power binding problem |
| 70 | -- | 87 | Patrick Schaumont, Doris Ching, Ingrid Verbauwhede. An interactive codesign environment for domain-specific coprocessors |
| 88 | -- | 103 | Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou. Reliable crosstalk-driven interconnect optimization |
| 104 | -- | 122 | Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi. Compile-time area estimation for LUT-based FPGAs |
| 123 | -- | 146 | Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau. Compilation framework for code size reduction using reduced bit-width ISAs (rISAs) |
| 147 | -- | 164 | Yi-Ping You, Chingren Lee, Jenq Kuen Lee. Compilers for leakage power reduction |
| 165 | -- | 185 | Zili Shao, Bin Xiao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha. Loop scheduling with timing and switching-activity minimization for VLIW DSP |
| 186 | -- | 212 | Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi. ILP models for simultaneous energy and transient power minimization during behavioral synthesis |
| 213 | -- | 227 | Muhammet Mustafa Ozdal, Martin D. F. Wong. Two-layer bus routing for high-speed printed circuit boards |
| 228 | -- | 250 | Mahmut T. Kandemir, J. Ramanujam, Ugur Sezer. Improving the energy behavior of block buffering using compiler optimizations |