| 1 | -- | 0 | Naehyuck Chang, David Z. Pan, Yuan Xie 0001. Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond |
| 2 | -- | 0 | Wei Hu, Dejun Mu, Jason Oberg, Baolei Mao, Mohit Tiwari, Timothy Sherwood, Ryan Kastner. Gate-Level Information Flow Tracking for Security Lattices |
| 3 | -- | 0 | Chun-Kai Wang, Yeh-Chi Chang, Hung-Ming Chen, Ching-Yu Chin. Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation |
| 4 | -- | 0 | Lingyi Liu, Shobha Vasudevan. Scaling Input Stimulus Generation through Hybrid Static and Dynamic Analysis of RTL |
| 5 | -- | 0 | Sharad Sinha, Thambipillai Srikanthan. Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective |
| 6 | -- | 0 | Graeme Gange, Harald Søndergaard, Peter J. Stuckey. Synthesizing Optimal Switching Lattices |
| 7 | -- | 0 | An-Che Cheng, Chia-Chih Jack Yen, Celina G. Val, Sam Bayless, Alan J. Hu, Iris Hui-Ru Jiang, Jing-Yang Jou. Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog |
| 8 | -- | 0 | Xueliang Li, Guihai Yan, Yinhe Han, Xiaowei Li 0001. SmartCap: Using Machine Learning for Power Adaptation of Smartphone's Application Processor |
| 9 | -- | 0 | Wen-Li Shih, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee. Compiler Optimization for Reducing Leakage Power in Multithread BSP Programs |
| 10 | -- | 0 | Bojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero. Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation |
| 11 | -- | 0 | Seungcheol Baek, Hyung Gyu Lee, Chrysostomos Nicopoulos, Jongman Kim. Designing Hybrid DRAM/PCM Main Memory Systems Utilizing Dual-Phase Compression |
| 12 | -- | 0 | Hsien-Kai Kuo, Bo-Cheng Charles Lai, Jing-Yang Jou. Reducing Contention in Shared Last-Level Cache for Throughput Processors |
| 13 | -- | 0 | Roopak Sinha, Alain Girault, Gregor Goessler, Partha S. Roop. A Formal Approach to Incremental Converter Synthesis for System-on-Chip Design |
| 14 | -- | 0 | Levent Aksoy, Paulo F. Flores, José C. Monteiro. Multiplierless Design of Folded DSP Blocks |
| 15 | -- | 0 | Mohamed Asan Basiri M., Sk. Noor Mahammad. An Efficient Hardware-Based Higher Radix Floating Point MAC Design |
| 16 | -- | 0 | Cristiana Bolchini, Chiara Sandionigi. Design of Hardened Embedded Systems on Multi-FPGA Platforms |