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21 | -- | 0 | Jin-Tai Yan. Performance-Driven Assignment of Buffered I/O Signals in Area-I/O Flip-Chip Designs |
22 | -- | 0 | Angeliki Kritikakou, Francky Catthoor, Vasilios I. Kelefouras, Costas E. Goutis. Array Size Computation under Uniform Overlapping and Irregular Accesses |
23 | -- | 0 | Youngsik Kim, Sungjoo Yoo, Sunggu Lee. Improving Write Performance by Controlling Target Resistance Distributions in MLC PRAM |
24 | -- | 0 | Dong Xiang, Kele Shen. A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing |
25 | -- | 0 | Zipeng Li, Tsung-Yi Ho, Krishnendu Chakrabarty. Optimization of 3D Digital Microfluidic Biochips for the Multiplexed Polymerase Chain Reaction |
26 | -- | 0 | Le Zhang, Vivek Sarin. Parallel Power Grid Analysis Based on Enlarged Partitions |
27 | -- | 0 | Song Jin, Songwei Pei, Yinhe Han, Huawei Li. A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands |
28 | -- | 0 | Mehdi Kamal, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram. Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions |
29 | -- | 0 | Guoqing Chen, Yi Xu, Xing Hu, Xiangyang Guo, Jun Ma, Yu Hu, Yuan Xie 0001. TSocket: Thermal Sustainable Power Budgeting |
30 | -- | 0 | Liang Chen, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori. Reliability-Aware Resource Allocation and Binding in High-Level Synthesis |
31 | -- | 0 | Jeremy Dubeuf, David Hély, Vincent Beroulle. ECDSA Passive Attacks, Leakage Sources, and Common Design Mistakes |
32 | -- | 0 | Martin Lukasiewycz, Philipp Mundhenk, Sebastian Steinhorst. Security-Aware Obfuscated Priority Assignment for Automotive CAN Platforms |
33 | -- | 0 | Chandra K. H. Suresh, Ozgur Sinanoglu, Sule Ozev. Adapting to Varying Distribution of Unknown Response Bits |
34 | -- | 0 | Jingweijia Tan, Zhi Li 0016, Mingsong Chen, Xin Fu. Exploring Soft-Error Robust and Energy-Efficient Register File in GPGPUs using Resistive Memory |
35 | -- | 0 | Irith Pomeranz. Design-for-Testability for Functional Broadside Tests under Primary Input Constraints |