Journal: ACM Trans. Design Autom. Electr. Syst.

Volume 21, Issue 4

55 -- 0Marcela Zuluaga, Peter Milder, Markus Püschel. Streaming Sorting Networks
56 -- 0Yue Zhao, Taeyoung Kim, Hosoon Shin, Sheldon X.-D. Tan, Xin Li, Hai-Bao Chen, Hai Wang. Statistical Rare-Event Analysis and Parameter Guidance by Elite Learning Sample Selection
57 -- 0Rickard Ewetz, Cheng-Kok Koh. Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Compression
58 -- 0Hassan Ghasemzadeh, Ramin Fallahzadeh, Roozbeh Jafari. A Hardware-Assisted Energy-Efficient Processing Model for Activity Recognition Using Wearables
59 -- 0Adam Teman, Davide Rossi, Pascal Meinerzhagen, Luca Benini, Andreas Burg. Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement
60 -- 0Swaminathan Narayanaswamy, Steffen Schlüter, Sebastian Steinhorst, Martin Lukasiewycz, Samarjit Chakraborty, Harry Ernst Hoster. On Battery Recovery Effect in Wireless Sensor Nodes
61 -- 0Dani A. Tannir, Ya Wang, Peng Li. Accurate Modeling of Nonideal Low-Power PWM DC-DC Converters Operating in CCM and DCM using Enhanced Circuit-Averaging Techniques
62 -- 0Sebastian Steinhorst, Matthias Kauer, Arne Meeuw, Swaminathan Narayanaswamy, Martin Lukasiewycz, Samarjit Chakraborty. Cyber-Physical Co-Simulation Framework for Smart Cells in Scalable Battery Packs
63 -- 0Ujjwal Guin, Qihang Shi, Domenic Forte, Mark M. Tehranipoor. FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs
64 -- 0William Lee, Vikas S. Vij, Kenneth S. Stevens. Timing Path-Driven Cycle Cutting for Sequential Controllers
65 -- 0Yang Xu, Jürgen Teich. Hierarchical Statistical Leakage Analysis and Its Application
66 -- 0Ramprasath S., Vinita Vasudevan. Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient
67 -- 0Hongfei Wang, R. D. (Shawn) Blanton. Ensemble Reduction via Logic Minimization
68 -- 0Irith Pomeranz. N-Detection Test Sets for Circuits with Multiple Independent Scan Chains
69 -- 0Jae Yeon Won, Paul V. Gratz, Srinivas Shakkottai, Jiang Hu. Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory
70 -- 0Ching-Hsuan Ho, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Suman Datta, Vijaykrishnan Narayanan. Area-Aware Decomposition for Single-Electron Transistor Arrays
71 -- 0Fubing Mao, Yi-Chung Chen, Wei Zhang, Hai Helen Li, Bingsheng He. Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration
72 -- 0Anna Bernasconi, Valentina Ciriani. Index-Resilient Zero-Suppressed BDDs: Definition and Operations

Volume 21, Issue 3

36 -- 0Evangeline F. Y. Young, Azadeh Davoodi. Preface to Special Section on New Physical Design Techniques for the Next Generation of Integration Technology
37 -- 0Nima Karimpour Darav, Andrew A. Kennings, Aysa Fakheri Tabrizi, David T. Westwick, Laleh Behjat. Eh?Placer: A High-Performance Modern Technology-Driven Placer
38 -- 0Vinicius S. Livramento, Renan Netto, Chrystian Guth, José Luís Güntzel, Luiz Cláudio Villar dos Santos. Clock-Tree-Aware Incremental Timing-Driven Placement
39 -- 0Po-Hsun Wu, Mark Po-Hung Lin, Xin Li, Tsung-Yi Ho. Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio Matching
40 -- 0Jinglei Huang, Song Chen, Wei Zhong, Wenchao Zhang, Shengxi Diao, Fujiang Lin. Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips with RF-Interconnect
41 -- 0Chang Xu, Guojie Luo, Peixin Li, Yiyu Shi, Iris Hui-Ru Jiang. Analytical Clustering Score with Application to Postplacement Register Clustering
42 -- 0Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan. PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning
43 -- 0Bei Yu, Kun Yuan, Jhih-Rong Gao, Shiyan Hu, David Z. Pan. EBL Overlapping Aware Stencil Planning for MCC System
44 -- 0Seungwon Kim, Seokhyeong Kang, Ki Jin Han, Youngmin Kim. Novel Adaptive Power-Gating Strategy and Tapered TSV Structure in Multilayer 3D IC
45 -- 0Gong Chen, Toru Fujimura, Qing Dong, Shigetoshi Nakatake, Bo Yang 0004. DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout
46 -- 0Chao Wang, Chuansheng Dong, Haibo Zeng, Zonghua Gu. Minimizing Stack Memory for Hard Real-Time Applications on Multicore Platforms with Partitioned Fixed-Priority or EDF Scheduling
47 -- 0Sungkwang Lee, Taemin Lee, Hyunsun Park, Junwhan Ahn, Sungjoo Yoo, Youjip Won, Sunggu Lee. Differential Write-Conscious Software Design on Phase-Change Memory: An SQLite Case Study
48 -- 0Xing Huang, Wenzhong Guo, Genggeng Liu, Guolong Chen. FH-OAOS: A Fast Four-Step Heuristic for Obstacle-Avoiding Octilinear Steiner Tree Construction
49 -- 0Sparsh Mittal. A Survey of Techniques for Cache Locking
50 -- 0Ramachandran Venkatasubramanian, Robert Elio, Sule Ozev. Process Independent Design Methodology for the Active RC and Single-Inverter-Based Rail Clamp
51 -- 0Sangmin Kim, Seokhyeong Kang, Youngsoo Shin. Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization
52 -- 0Zhiliang Qian, Paul Bogdan, Chi-Ying Tsui, Radu Marculescu. Performance Evaluation of NoC-Based Multicore Systems: From Traffic Analysis to NoC Latency Modeling
53 -- 0Hany Kashif, Hiren D. Patel, Sebastian Fischmeister. Path Selection for Real-Time Communication on Priority-Aware NoCs
54 -- 0Chuangwen Liu, Peishan Tu, Pangbo Wu, Haomo Tang, Yande Jiang, Jian Kuang 0001, Evangeline F. Y. Young. An Effective Chemical Mechanical Polishing Fill Insertion Approach

Volume 21, Issue 2

19 -- 0Daming Zhang, Shuangchen Li, Yongpan Liu, Xiaobo Sharon Hu, Xinyu He, Yining Zhang, Pei Zhang, Huazhong Yang. A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming Applications
20 -- 0Laurence Pierre. Auxiliary Variables in Temporal Specifications: Semantic and Practical Analysis for System-Level Requirements
21 -- 0Jin-Tai Yan. Performance-Driven Assignment of Buffered I/O Signals in Area-I/O Flip-Chip Designs
22 -- 0Angeliki Kritikakou, Francky Catthoor, Vasilios I. Kelefouras, Costas E. Goutis. Array Size Computation under Uniform Overlapping and Irregular Accesses
23 -- 0Youngsik Kim, Sungjoo Yoo, Sunggu Lee. Improving Write Performance by Controlling Target Resistance Distributions in MLC PRAM
24 -- 0Dong Xiang, Kele Shen. A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing
25 -- 0Zipeng Li, Tsung-Yi Ho, Krishnendu Chakrabarty. Optimization of 3D Digital Microfluidic Biochips for the Multiplexed Polymerase Chain Reaction
26 -- 0Le Zhang, Vivek Sarin. Parallel Power Grid Analysis Based on Enlarged Partitions
27 -- 0Song Jin, Songwei Pei, Yinhe Han, Huawei Li. A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands
28 -- 0Mehdi Kamal, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram. Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions
29 -- 0Guoqing Chen, Yi Xu, Xing Hu, Xiangyang Guo, Jun Ma, Yu Hu, Yuan Xie 0001. TSocket: Thermal Sustainable Power Budgeting
30 -- 0Liang Chen, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori. Reliability-Aware Resource Allocation and Binding in High-Level Synthesis
31 -- 0Jeremy Dubeuf, David Hély, Vincent Beroulle. ECDSA Passive Attacks, Leakage Sources, and Common Design Mistakes
32 -- 0Martin Lukasiewycz, Philipp Mundhenk, Sebastian Steinhorst. Security-Aware Obfuscated Priority Assignment for Automotive CAN Platforms
33 -- 0Chandra K. H. Suresh, Ozgur Sinanoglu, Sule Ozev. Adapting to Varying Distribution of Unknown Response Bits
34 -- 0Jingweijia Tan, Zhi Li 0016, Mingsong Chen, Xin Fu. Exploring Soft-Error Robust and Energy-Efficient Register File in GPGPUs using Resistive Memory
35 -- 0Irith Pomeranz. Design-for-Testability for Functional Broadside Tests under Primary Input Constraints

Volume 21, Issue 1

1 -- 0Debashri Roy, Prasun Ghosal, Saraju P. Mohanty. FuzzRoute: A Thermally Efficient Congestion-Free Global Routing Method for Three-Dimensional Integrated Circuits
2 -- 0Ye Zhang, Wai-Shing Luk, Yunfeng Yang, Hai Zhou, Changhao Yan, David Z. Pan, Xuan Zeng. Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography
3 -- 0Hu Chen, Sanghamitra Roy, Koushik Chakraborty. DARP-MP: Dynamically Adaptable Resilient Pipeline Design in Multicore Processors
4 -- 0Myungsun Kim, Jinkyu Koo, Hyojung Lee, James R. Geraci. Memory Management Scheme to Improve Utilization Efficiency and Provide Fast Contiguous Allocation without a Statically Reserved Area
5 -- 0Fabian Oboril, Mehdi Baradaran Tahoori. Exploiting Instruction Set Encoding for Aging-Aware Microprocessor Design
6 -- 0Ankit More, Baris Taskin. Locality-Aware Network Utilization Balancing in NoCs
7 -- 0Hsiang-Yun Cheng, Mary Jane Irwin, Yuan Xie 0001. Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference
8 -- 0Gilberto Ochoa-Ruiz, Sébastien Guillet, Florent de Lamotte, Éric Rutten, El-Bay Bourennane, Jean-Philippe Diguet, Guy Gogniat. An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems
9 -- 0Shih-Hsu Huang, Hua-Hsin Yeh, Yow-Tyng Nieh. Clock Period Minimization with Minimum Leakage Power
10 -- 0Anupama R. Subramaniam, Janet Roveda, Yu Cao. A Finite-Point Method for Efficient Gate Characterization Under Multiple Input Switching
11 -- 0Dongha Jung, Hokyoon Lee, Seon Wook Kim. Lowering Minimum Supply Voltage for Power-Efficient Cache Design by Exploiting Data Redundancy
12 -- 0Ying Qin, ShengYu Shen, Qingbo Wu, Huadong Dai, Yan Jia. Complementary Synthesis for Encoder with Flow Control Mechanism
13 -- 0Irith Pomeranz. Enhanced Test Compaction for Multicycle Broadside Tests by Using State Complementation
14 -- 0Seetal Potluri, Satya Trinadh, Ch. Sobhan Babu, V. Kamakoti, Nitin Chandrachoodan. DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing
15 -- 0Chien-Chih Huang, Chin-Long Wey, Jwu-E Chen, Pei-Wen Luo. Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs
16 -- 0Jin Sun, Claudio Talarico, Priyank Gupta, Janet Roveda. A New Uncertainty Budgeting-Based Method for Robust Analog/Mixed-Signal Design
17 -- 0Debasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman, Krishnendu Chakrabarty, Bhargab B. Bhattacharya. Offline Washing Schemes for Residue Removal in Digital Microfluidic Biochips
18 -- 0Chung-Wei Lin, Bowen Zheng, Qi Zhu, Alberto L. Sangiovanni-Vincentelli. Security-Aware Design Methodology and Optimization for Automotive Systems