External Links

    Journal: ACM Trans. Design Autom. Electr. Syst.

    Volume 4, Issue 4

    351 -- 375Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi. Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
    376 -- 404Kyumyung Choi, Steven P. Levitan. A flexible datapath allocation method for architectural synthesis
    405 -- 429Inki Hong, Miodrag Potkonjak, Ramesh Karri. Power optimization using divide-and-conquer techniques for minimization of the number of operations
    430 -- 459Miodrag Potkonjak, Wayne Wolf. A methodology and algorithms for the design of hard real-time multitasking ASICs

    Volume 4, Issue 3

    231 -- 256Wei-Kai Cheng, Youn-Long Lin. Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining
    257 -- 279Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe. Performance estimation of embedded software with instruction cache modeling
    280 -- 312C.-J. Richard Shi, Michael W. Tian. Simulation and sensitivity of linear analog circuits under parameter variations by Robust interval analysis
    313 -- 350Bernd Wurth, Ulf Schlichtmann, Klaus Eckl, Kurt Antreich. Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs

    Volume 4, Issue 2

    123 -- 193Christoph Kern, Mark R. Greenstreet. Formal verification in hardware design: a survey
    194 -- 218Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang. BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults
    219 -- 230Mitchell A. Thornton, V. S. S. Nair. Behavioral synthesis of combinational logic using spectral-based heuristics

    Volume 4, Issue 1

    1 -- 11Michael Gasteier, Manfred Glesner. Bus-based communication synthesis on system level
    12 -- 38Stan Y. Liao, Srinivas Devadas, Kurt Keutzer. A text-compression-based method for code size minimization in embedded systems
    39 -- 51Xiaoyu Song, Yuke Wang. On the crossing distribution problem
    52 -- 69Jyh-Mou Tseng, Jing-Yang Jou. Two-level logic minimization for low power
    70 -- 96Frank Vahid. Procedure cloning: a transformation for improved system-level functional partitioning
    97 -- 121Qi Wang, Sarma B. K. Vrudhula, Gary K. H. Yeap, Shantanu Ganguly. Power reduction and power-delay trade-offs using logic transformations
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