Journal: ACM Trans. Design Autom. Electr. Syst.

Volume 9, Issue 4

385 -- 418Ali Dasdan. Experimental analysis of the fastest optimum cycle ratio and mean algorithms
419 -- 440Arijit Ghosh, Tony Givargis. Cache optimization for embedded processor cores: An analytical approach
441 -- 470Sumit Gupta, Rajesh K. Gupta, Nikil D. Dutt, Alexandru Nicolau. Coordinated parallelizing compiler optimizations and high-level synthesis
471 -- 499Érika F. Cota, Luigi Carro, Marcelo Lubaszewski. Reusing an on-chip network for the test of core-based systems
500 -- 516C. V. Krishna, Abhijit Jas, Nur A. Touba. Achieving high encoding efficiency with partial dynamic LFSR reseeding
517 -- 528William N. N. Hung, Xiaoyu Song, El Mostapha Aboulhamid, Andrew A. Kennings, Alan J. Coppola. Segmented channel routability via satisfiability

Volume 9, Issue 3

273 -- 289Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi. A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints
290 -- 309Kevin M. Lepak, Min Xu, Jun Chen, Lei He. Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
310 -- 332Juan de Vicente, Juan Lanchares, Román Hermida. Annealing placement by thermodynamic combinatorial optimization
333 -- 353Andreas Dandalis, Viktor K. Prasanna. An adaptive cryptographic engine for internet protocol security architectures
354 -- 384Jun Yang, Rajiv Gupta, Chuanjun Zhang. Frequent value encoding for low power data buses

Volume 9, Issue 2

133 -- 158Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas. Storage requirement estimation for optimized design of data intensive applications
159 -- 198Sagar S. Sabade, D. M. H. Walker. I::DDX::-based test methods: A survey
199 -- 211Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu. Stairway compaction using corner block list and its applications with rectilinear blocks
212 -- 237Praveen K. Murthy, Shuvra S. Bhattacharyya. Buffer merging - a powerful technique for reducing memory requirements of synchronous dataflow specifications
238 -- 271Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri. A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications

Volume 9, Issue 1

1 -- 32Annette Bunker, Ganesh Gopalakrishnan, Sally A. McKee. Formal hardware specification languages for protocol compliance verification
33 -- 51Hao Li, Srinivas Katkoori, Wai-Kei Mak. Power minimization algorithms for LUT-based FPGA technology mapping
52 -- 74Jeonghun Cho, Yunheung Paek, David B. Whalley. Fast memory bank assignment for fixed-point digital signal processors
75 -- 104Sandip Das, Susmita Sur-Kolay, Bhargab B. Bhattacharya. Manhattan-diagonal routing in channels and switchboxes
105 -- 132Lieh-Ming Wu, Kuochen Wang, Chuang-Yi Chiu. A BNF-based automatic test program generator for compatible microprocessor verification