Journal: TRETS

Volume 8, Issue 3

14 -- 0Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson. The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware
15 -- 0Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu, Oliver Pell. Automating Elimination of Idle Functions by Runtime Reconfiguration
16 -- 0Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Wei He. Exploiting FPGA Block Memories for Protected Cryptographic Implementations
17 -- 0Juan Fernando Eusse Giraldo, Christopher Williams, Rainer Leupers. CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design
18 -- 0Anup Das 0001, Amit Kumar Singh, Akash Kumar. Execution Trace-Driven Energy-Reliability Optimization for Multimedia MPSoCs
19 -- 0Yu Ren, Leibo Liu, Shouyi Yin, Jie Han, Shaojun Wei. Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm
20 -- 0Roland Dobai, Lukás Sekanina. Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware