Journal: TRETS

Volume 8, Issue 4

21 -- 0Robert Kirchgessner, Alan D. George, Greg Stitt. Low-Overhead FPGA Middleware for Application Portability and Productivity
22 -- 0Matthew Jacobsen, Dustin Richmond, Matthew Hogains, Ryan Kastner. RIFFA 2.1: A Reusable Integration Framework for FPGA Accelerators
23 -- 0David B. Thomas. The Table-Hadamard GRNG: An Area-Efficient FPGA Gaussian Random Number Generator
24 -- 0Zheming Jin, Jason D. Bakos. Memory Interface Design for 3D Stencil Kernels on a Massively Parallel Memory System
25 -- 0Guangming Tan, Chunming Zhang, Wendi Wang, Peiheng Zhang. SuperDragon: A Heterogeneous Parallel System for Accelerating 3D Reconstruction of Cryo-Electron Microscopy Images
26 -- 0Alexander Biedermann, Sorin A. Huss, Adeel Israr. Safe Dynamic Reshaping of Reconfigurable MPSoC Embedded Systems for Self-Healing and Self-Adaption Purposes

Volume 8, Issue 3

14 -- 0Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson. The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware
15 -- 0Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu, Oliver Pell. Automating Elimination of Idle Functions by Runtime Reconfiguration
16 -- 0Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Wei He. Exploiting FPGA Block Memories for Protected Cryptographic Implementations
17 -- 0Juan Fernando Eusse Giraldo, Christopher Williams, Rainer Leupers. CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design
18 -- 0Anup Das 0001, Amit Kumar Singh, Akash Kumar. Execution Trace-Driven Energy-Reliability Optimization for Multimedia MPSoCs
19 -- 0Yu Ren, Leibo Liu, Shouyi Yin, Jie Han, Shaojun Wei. Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm
20 -- 0Roland Dobai, Lukás Sekanina. Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware

Volume 8, Issue 2

6 -- 0Kan Shi, David Boland, George A. Constantinides. Imprecise Datapath Design: An Overclocking Approach
7 -- 0Louis Woods, Gustavo Alonso, Jens Teubner. Parallelizing Data Processing on FPGAs with Shifter Lists
8 -- 0João M. P. Cardoso, Pedro C. Diniz, Katherine (Compton) Morrow. Guest Editorial FPL 2013
9 -- 0Ricardo S. Ferreira, Luciana Rocha, André G. Santos, José Augusto Miranda Nacif, Stephan Wong, Luigi Carro. A Runtime FPGA Placement and Routing Using Low-Complexity Graph Traversal
10 -- 0Kevin E. Murray, Scott Whitty, Suya Liu, Jason Luu, Vaughn Betz. Timing-Driven Titan: Enabling Large Benchmarks and Exploring the Gap between Academic and Commercial CAD
11 -- 0Lin Gan, Haohuan Fu, Wayne Luk, Chao Yang, Wei Xue, Xiaomeng Huang, Youhui Zhang, Guangwen Yang. Solving the Global Atmospheric Equations through Heterogeneous Reconfigurable Platforms
12 -- 0Anup Das 0001, Shyamsundar Venkataraman, Akash Kumar. Autonomous Soft-Error Tolerance of FPGA Configuration Bits
13 -- 0Zsolt István, Gustavo Alonso, Michaela Blott, Kees A. Vissers. A Hash Table for Line-Rate Data Processing

Volume 8, Issue 1

1 -- 0Stefano Di Carlo, Giulio Gambardella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta. SATTA: A Self-Adaptive Temperature-Based TDF Awareness Methodology for Dynamically Reconfigurable FPGAs
2 -- 0Patrick Cooke, Jeremy Fowers, Greg Brown, Greg Stitt. A Tradeoff Analysis of FPGAs, GPUs, and Multicores for Sliding-Window Applications
3 -- 0Heather M. Quinn, Diane Roussel-Dupre, Michael P. Caffrey, Paul S. Graham, Michael J. Wirthlin, Keith Morgan, Anthony Salazar, Tony Nelson, William Howes, Darrel Eric Johnson, Jonathan M. Johnson, Brian H. Pratt, Nathan Rollins, Jim Krone. The Cibola Flight Experiment
4 -- 0Tom Davidson, Elias Vansteenkiste, Karel Heyse, Karel Bruneel, Dirk Stroobandt. Identification of Dynamic Circuit Specialization Opportunities in RTL Code
5 -- 0Xabier Iturbe, Khaled Benkrid, Chuan Hong, Ali Ebrahim, Raul Torrego, Tughrul Arslan. Microkernel Architecture and Hardware Abstraction Layer of a Reliable Reconfigurable Real-Time Operating System (R3TOS)