| 525 | -- | 537 | Subodh Gupta, Farid N. Najm. Energy and peak-current per-cycle estimation at RTL |
| 538 | -- | 557 | Anand Raghunathan, Sujit Dey, Niraj K. Jha. High-level macro-modeling and estimation techniques for switching activity and power consumption |
| 558 | -- | 567 | Sanjukta Bhanja, N. Ranganathan. Switching activity estimation of VLSI circuits using Bayesian networks |
| 568 | -- | 580 | Yen-Jen Chang, Shanq-Jang Ruan, Feipei Lai. Design and analysis of low-power cache using two-level filter scheme |
| 581 | -- | 589 | Chua-Chin Wang, Ya-Hsin Hsueh, Ying-Pei Chen. An area-saving decoder structure for ROMs |
| 590 | -- | 600 | Byung-Do Yang, Lee-Sup Kim. A low-power charge-recycling ROM architecture |
| 601 | -- | 615 | George Hadjiyiannis, Srinivas Devadas. Techniques for accurate performance evaluation in architecture exploration |
| 616 | -- | 626 | Y. Elboim, Avinoam Kolodny, Ran Ginosar. A clock-tuning circuit for system-on-chip |
| 627 | -- | 650 | Mohammad M. Mansour, Naresh R. Shanbhag. VLSI architectures for SISO-APP decoders |
| 651 | -- | 658 | Shih-Chang Hsia. Parallel VLSI design for a real-time video-impulse noise-reduction processor |
| 659 | -- | 678 | Gaye Lightbody, Roger Woods, Richard Walke. Design of a parameterizable silicon intellectual property core for QR-based RLS filtering |
| 679 | -- | 686 | Jai-Ming Lin, Yao-Wen Chang, Shih-Ping Lin. Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme |
| 687 | -- | 690 | Hong Sik Kim, YongJoon Kim, Sungho Kang. Test-decompression mechanism using a variable-length multiple-polynomial LFSR |
| 691 | -- | 700 | Ting-Yuan Wang, Charlie Chung-Ping Chen. Thermal-ADI - a linear-time chip-level dynamic thermal-simulation algorithm based on alternating-direction-implicit (ADI) method |
| 701 | -- | 715 | Navid Azizi, Farid N. Najm, Andreas Moshovos. Low-leakage asymmetric-cell SRAM |
| 716 | -- | 730 | Saibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy. Gate leakage reduction for scaled devices using transistor stacking |
| 731 | -- | 737 | Peter Grun, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau. RTGEN-an algorithm for automatic generation of reservation tables from architectural descriptions |
| 737 | -- | 740 | Chua-Chin Wang, Po-Ming Lee, Jun-Jie Wang, Chenn-Jung Huang. Design of a cycle-efficient 64-b/32-b integer divisor using a table-sharing algorithm |
| 741 | -- | 744 | Sujit T. Zachariah, Sreejit Chakravarty. Algorithm to extract two-node bridges |
| 744 | -- | 748 | T. Thorp, D. Liu, P. Trivedi. Analysis of blocking dynamic circuits |