| 753 | -- | 754 | Vivek De, Luca Benini. Guest editorial |
| 755 | -- | 761 | Hyunsik Im, T. Inukai, H. Gomyo, T. Hiramoto, T. Sakurai. VTCMOS characteristics and its optimum conditions predicted by a compact analytical model |
| 762 | -- | 777 | Joong-Seok Moon, William C. Athas, Sigfrid D. Soli, Jeffrey T. Draper, Peter A. Beerel. Voltage-pulse driven harmonic resonant rail drivers for low-power applications |
| 778 | -- | 788 | Victor V. Zyuban. Optimization of scannable latches for low energy |
| 789 | -- | 800 | Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose, Peter M. Kogge. Energy-efficient issue queue design |
| 801 | -- | 811 | Baruch Solomon, Avi Mendelson, Ronny Ronen, Doron Orenstein, Yoav Almog. Micro-operation cache: a power aware frontend for variable instruction length ISA |
| 812 | -- | 826 | Johan A. Pouwelse, Koen Langendoen, Henk J. Sips. Application-directed voltage scaling |
| 827 | -- | 834 | Mahesh Mamidipaka, Daniel S. Hirschberg, Nikil D. Dutt. Adaptive low-power address encoding techniques using self-organizing lists |
| 835 | -- | 838 | M. A. I. Mostafa, Sherif H. K. Embabi, Mostafa Elmala. A 60-dB 246-MHz CMOS variable gain amplifier for subsampling GSM receivers |
| 839 | -- | 852 | Mandeep Singh, Israel Koren. Fault-sensitivity analysis and reliability enhancement of analog-to-digital converters |
| 853 | -- | 862 | Sungbae Hwang, Jacob A. Abraham. Test data compression and test time reduction using an embedded microprocessor |
| 863 | -- | 870 | Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Vivek De. Multiple-parameter CMOS IC testing with increased sensitivity for I::DDQ:: |
| 871 | -- | 878 | Mohammad Maymandi-Nejad, Manoj Sachdev. A digitally programmable delay element: design and analysis |
| 879 | -- | 887 | Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang. Coupling delay optimization by temporal decorrelation using dual threshold voltage technique |
| 888 | -- | 899 | T. Chen, S. Naffziger. Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation |
| 900 | -- | 908 | Yehea I. Ismail. Improved model-order reduction by using spacial information in moments |
| 909 | -- | 920 | Lucian Codrescu, S. Nugent, James D. Meindl, D. Scott Wills. Modeling technology impact on cluster microprocessor performance |
| 921 | -- | 927 | Ashok K. Murugavel, N. Ranganathan. Petri net modeling of gate and interconnect delays for power estimation |
| 928 | -- | 938 | Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda. Memory allocation and mapping in high-level synthesis - an integrated approach |
| 939 | -- | 943 | Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo. A high-speed energy-efficient 64-bit reconfigurable binary adder |
| 943 | -- | 951 | Tiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne Wolf. A dictionary-based en/decoding scheme for low-power data buses |
| 951 | -- | 954 | Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura. Reduction of coupling effects by optimizing the 3-D configuration of the routing grid |
| 955 | -- | 960 | Sandeep Koranne. Design of reconfigurable access wrappers for embedded core based SoC test |