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| 314 | -- | 324 | Lu Peng, Jih-Kwon Peir, Qianrong Ma, Konrad Lai. Address-free memory access based on program syntax correlation of loads and stores |
| 325 | -- | 335 | John Patrick McGregor, Ruby B. Lee. Architectural techniques for accelerating subword permutations with repetitions |
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| 354 | -- | 363 | Amit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska. PITIA: an FPGA for throughput-intensive applications |
| 364 | -- | 375 | Chun-Gi Lyuh, Taewhan Kim. High-level synthesis for low power based on network flow method |
| 376 | -- | 385 | Frederik Vermeulen, Francky Catthoor, Lode Nachtergaele, Diederik Verkest, Hugo De Man. Power-efficient flexible processor architecture for embedded applications |
| 386 | -- | 405 | Abderrahim Doumar, Hideo Ito. Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey |
| 406 | -- | 417 | Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III. Current-mode signaling in deep submicrometer global interconnects |
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| 434 | -- | 445 | Lei Wang, Naresh R. Shanbhag. Low-power MIMO signal processing |
| 446 | -- | 450 | Kostas Masselos, Panagiotis Merakos, S. Theoharis, Thanos Stouraitis, Constantinos E. Goutis. Power efficient data path synthesis of sum-of-products computations |
| 451 | -- | 460 | Yu-Liang Wu, Chak-Chung Cheung, David Ihsin Cheng, Hongbing Fan. Further improve circuit partitioning using GBAW logic perturbation techniques |
| 461 | -- | 473 | Lauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer. Buffer delay change in the presence of power and ground noise |
| 474 | -- | 484 | Jin-Hua Hong, Cheng-Wen Wu. Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth s algorithm |
| 485 | -- | 498 | Xuejun Liang, Jack S. N. Jean. Mapping of generalized template matching onto reconfigurable computers |
| 499 | -- | 510 | J. L. Nunez, S. Jones. Gbit/s lossless data compression hardware |
| 511 | -- | 514 | Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Andrew A. Kennings, Alan J. Coppola. Board-level multiterminal net assignment for the partial cross-bar architecture |
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