| 1 | -- | 11 | N. Ranganathan. Editorial |
| 12 | -- | 27 | Baris Taskin, Ivan S. Kourtev. Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits |
| 28 | -- | 41 | Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang. Timing modeling and optimization under the transmission line model |
| 42 | -- | 51 | Ankur Srivastava, Ryan Kastner, Chunhong Chen, Majid Sarrafzadeh. Timing driven gate duplication |
| 52 | -- | 66 | R. Galli, Alexandre F. Tenca. A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm |
| 67 | -- | 78 | Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Ivan S. Kourtev, Eby G. Friedman. Substrate coupling in digital circuits in mixed-signal smart-power systems |
| 79 | -- | 95 | Antonio H. Chan, Gordon W. Roberts. A jitter characterization system using a component-invariant Vernier delay line |
| 96 | -- | 107 | Tajana Simunic, Stephen P. Boyd, Peter W. Glynn. Managing power consumption in networks on chips |
| 108 | -- | 119 | Girish Varatkar, Radu Marculescu. On-chip traffic modeling and synthesis for MPEG-2 video applications |
| 120 | -- | 122 | Roman L. Lysecky, Susan Cotterell, Frank Vahid. A fast on-chip profiler memory using a pipelined binary tree |