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    Journal: IEEE Trans. VLSI Syst.

    Volume 12, Issue 9

    885 -- 894Rouwaida Kanj, Elyse Rosenbaum. Critical evaluation of SOI design guidelines
    895 -- 900Chua-Chin Wang, Yih-Long Tseng, Hsien-Chih She, Chih-Chen Li, Ron Hu. A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula
    901 -- 909Chua-Chin Wang, Yih-Long Tseng, Hon-Yuan Leo, Ron Hu. A 4-kB 500-MHz 4-T CMOS SRAM using low-V::THN:: bitline drivers and high-V::THP:: latches
    910 -- 925Li Ding 0002, Pinaki Mazumder. On circuit techniques to improve noise immunity of CMOS dynamic logic
    926 -- 936Sarvesh H. Kulkarni, Dennis Sylvester. High performance level conversion for dual V::DD:: design
    937 -- 946Changbo Long, Lei He. Distributed sleep transistor network for power reduction
    947 -- 956L. T. Clark, M. Morrow, W. Brown. Reverse-body bias and supply collapse for low effective standby power
    957 -- 967Xinmiao Zhang, Keshab K. Parhi. High-speed VLSI architectures for the AES algorithm
    968 -- 977J. Kaza, C. Chakrabarti. Design and implementation of low-energy turbo decoders
    978 -- 994Mathew A. Sacker, Andrew D. Brown, Andrew J. Rushton, Peter R. Wilson. A behavioral synthesis system for asynchronous circuits
    995 -- 999Stefania Perri, Pasquale Corsonello, Maria Antonia Iachino, Marco Lanuzza, Giuseppe Cocorullo. Variable precision arithmetic circuits for FPGA-based multimedia processors

    Volume 12, Issue 8

    793 -- 811Paul Pop, Petru Eles, Zebo Peng, Traian Pop. Scheduling and mapping in an incremental design methodology for distributed real-time embedded systems
    812 -- 826Peter Petrov, Alex Orailoglu. Low-power instruction bus encoding for embedded processors
    827 -- 836Yen-Jen Chang, Feipei Lai, Chia-Lin Yang. Zero-aware asymmetric SRAM cell for reducing cache power in writing zero
    837 -- 846Naehyuck Chang, Inseok Choi, Hojun Shim. DLS: dynamic backlight luminance scaling of liquid crystal display
    847 -- 856Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar. Asynchronous gate-diffusion-input (GDI) circuits
    857 -- 873Tiberiu Chelcea, Steven M. Nowick. Robust interfaces for mixed-timing systems
    874 -- 877Shinn-Ying Ho, Shinn-Jang Ho, Yi-Kuang Lin, W. C.-C. Chu. An orthogonal simulated annealing algorithm for large floorplanning problems
    876 -- 880Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards. A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability

    Volume 12, Issue 7

    676 -- 685Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, Petri Liuha. Multiple-symbol parallel decoding for variable length codes
    686 -- 691Sumio Morioka, Akashi Satoh. A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture
    691 -- 696Arif Ishaq Abou-Seido, Brian Nowak, Chris Chong-Nuen Chu. Fitted Elmore delay: a simple and accurate interconnect delay model
    696 -- 699Ivan Blunno, Luciano Lavagno. Designing an asynchronous microcontroller using Pipefitter
    701 -- 710Yongchul Song, Beomsup Kim. Quadrature direct digital frequency synthesizers using interpolation-based angle rotation
    711 -- 726Jian Liang, Andrew Laffely, S. Srinivasan, Russell Tessier. An architecture and compiler for scalable on-chip communication
    727 -- 734Arne Halaas, Børge Svingen, Magnar Nedland, Pål Sætrom, Ola R. Snøve Jr., Olaf René Birkeland. A recursive MISD architecture for pattern matching
    735 -- 745Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho. Placement constraints in floorplan design
    746 -- 755Yi Zhao, Sujit Dey, Li Chen. Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses
    756 -- 765Sule Ozev, Alex Orailoglu. Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead
    766 -- 775Keoncheol Shin, Taewhan Kim. Tight integration of timing-driven synthesis and placement of parallel multiplier circuits
    775 -- 781Abhijit Jas, Bahram Pouya, Nur A. Touba. Test data compression technique for embedded cores using virtual scan chains
    780 -- 788Irith Pomeranz, Sudhakar M. Reddy. Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations

    Volume 12, Issue 6

    553 -- 561Jennifer L. Wong, Gang Qu, Miodrag Potkonjak. Power minimization in QoS sensitive systems
    562 -- 572Saraju P. Mohanty, Nagarajan Ranganathan. A framework for energy and transient power reduction during behavioral synthesis
    573 -- 589Noureddine Chabini, Wayne Wolf. Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling
    590 -- 602Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha. Input space adaptive design: a high-level methodology for optimizing energy and performance
    603 -- 621Mahmoud Meribout, Masato Motomura. Efficient metrics and high-level synthesis for dynamically reconfigurable logic
    622 -- 635Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers. Pel reconstruction on FPGA-augmented TriMedia
    636 -- 641J. V. Deodhar, Spyros Tragoudas. Implicit deductive fault simulation for complex delay fault models
    642 -- 651Jun Jin Kong, Keshab K. Parhi. Low-latency architectures for high-throughput rate Viterbi decoders
    652 -- 657R. Singh, N. Bhat. An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs
    657 -- 661Imed Ben Dhaou, Hannu Tenhunen. Efficient library characterization for high-level power estimation
    662 -- 669A. Valentian, O. Thomas, Andrei Vladimirescu, Amara Amara. Modeling subthreshold SOI logic for static timing analysis

    Volume 12, Issue 5

    453 -- 463Pingshan Wang, G. Pei, E. C.-C. Kan. Pulsed wave interconnect
    464 -- 476Himanshu Kaul, Dennis Sylvester. Low-power on-chip communication based on transition-aware global signaling (TAGS)
    477 -- 484Peiyi Zhao, Tarek Darwish, Magdy A. Bayoumi. High-performance and low-power conditional discharge flip-flop
    485 -- 496Volkan Kursun, Eby G. Friedman. Sleep switch dual threshold Voltage domino logic with reduced standby leakage current
    497 -- 510Byonghyo Shim, Srinivasa R. Sridhara, Naresh R. Shanbhag. Reliable low-power digital signal processing via reduced precision redundancy
    511 -- 521Nhon T. Quach, Naofumi Takagi, Michael J. Flynn. Systematic IEEE rounding method for high-speed floating-point multipliers
    522 -- 531Kyung-Ju Cho, Kwang-Chul Lee, Jin-Gyun Chung, Keshab K. Parhi. Design of low-error fixed-width modified booth multiplier
    532 -- 537YongJoon Kim, Hyun-Don Kim, Sungho Kang. A new maximal diagnosis algorithm for interconnect test
    538 -- 545Farhad H. A. Asgari, Manoj Sachdev. A low-power reduced swing global clocking methodology
    545 -- 549Yanni Chen, Keshab K. Parhi. Small area parallel Chien search architectures for long BCH codes

    Volume 12, Issue 4

    337 -- 338Jeff Alan Davis. Guest Editorial
    339 -- 348Joni Dambre, Dirk Stroobandt, Jan Van Campenhout. Toward the accurate prediction of placement wire length distributions in VLSI circuits
    349 -- 358Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni. An electromigration and thermal model of power wires for a priori high-level reliability prediction
    359 -- 366Shamik Das, Anantha Chandrakasan, Rafael Reif. Calibration of Rent s rule models for three-dimensional integrated circuits
    367 -- 372James W. Joyner, Payman Zarkesh-Ha, James D. Meindl. Global interconnect design in a three-dimensional system-on-a-chip
    373 -- 380Suhrid A. Wadekar, Alice C. Parker. Interconnect-based system-level energy and power prediction to guide architecture exploration
    381 -- 385PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia. On metrics for comparing interconnect estimation methods for FPGAs
    386 -- 394Andrey V. Mezhiba, Eby G. Friedman. Scaling trends of on-chip power distribution noise
    395 -- 407Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim. Analytical models and algorithms for the efficient signal integrity verification of inductance-effect-prominent multicoupled VLSI circuit interconnects
    408 -- 419Iouliia Skliarova, António de Brito Ferrari. A software/reconfigurable hardware SAT solver
    420 -- 436Khaled Benkrid, Danny Crookes. From application descriptions to hardware in seconds: a logic-based approach to bridging the gap
    437 -- 447Shizhong Mei, Yehea I. Ismail. Modeling skin and proximity effects with reduced realizable RL circuits

    Volume 12, Issue 3

    233 -- 234Christian Piguet, Narayanan Vijaykrishnan. Guest Editorial
    235 -- 244Amaury Nève, Helmut Schettler, Thomas Ludwig 0004, Denis Flandre. Power-delay product minimization in high-performance 64-bit carry-select adders
    245 -- 254Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar. DCG: deterministic clock-gating for low-power microprocessor design
    255 -- 268Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii. Memory energy minimization by data compression: algorithms, architectures and implementation
    269 -- 280Edgar G. Daylight, David Atienza, Arnout Vandecappelle, Francky Catthoor, José M. Mendías. Memory-access-aware data structure transformations for embedded software with dynamic data accesses
    281 -- 287Mahmut T. Kandemir, Ismail Kadayif, Alok N. Choudhary, Ibrahim Kolcu. Compiler-directed scratch pad memory optimization for embedded multiprocessors
    288 -- 298Elias Ahmed, Jonathan Rose. The effect of LUT and cluster size on deep-submicron FPGA performance and density
    299 -- 311Atul Maheshwari, Wayne Burleson, Russell Tessier. Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits
    312 -- 324Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Vikram Saxena, Steven Parkes, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, David Zaretsky, R. Anderson, J. R. Uribe. Overview of a compiler for synthesizing MATLAB programs onto FPGAs
    325 -- 329Aristides Efthymiou, Jim D. Garside. A CAM with mixed serial-parallel comparison for use in low energy caches

    Volume 12, Issue 2

    129 -- 130Christian Piguet, Narayanan Vijaykrishnan. Guest Editorial
    131 -- 139Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester. Statistical analysis of subthreshold leakage current for VLSI circuits
    140 -- 154Afshin Abdollahi, Farzan Fallah, Massoud Pedram. Leakage current reduction in CMOS VLSI circuits by input vector control
    155 -- 166Dongwoo Lee, David Blaauw, Dennis Sylvester. Gate oxide leakage current analysis and reduction for VLSI circuits
    167 -- 184Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge. Circuit and microarchitectural techniques for reducing cache leakage power
    185 -- 195Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic. Level conversion for dual-supply systems
    196 -- 205Narender Hanchate, Nagarajan Ranganathan. LECTOR: a technique for leakage reduction in CMOS circuits
    206 -- 217Scott Hauck, Thomas W. Fry, Matthew M. Hosler, Jeffrey P. Kao. The Chimaera reconfigurable functional unit
    218 -- 226Meng-Da Yang, An-Yeu Wu, Jyh-Ting Lai. High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme

    Volume 12, Issue 12

    1263 -- 1276Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty. SOC test planning using virtual test access architectures
    1277 -- 1283Abhijit Jas, C. V. Krishna, Nur A. Touba. Weighted pseudorandom hybrid BIST
    1284 -- 1294Miron Abramovici, Charles E. Stroud, John M. Emmert. Online BIST and BIST-based diagnosis of FPGA logic blocks
    1295 -- 1306Magdy A. El-Moursy, Eby G. Friedman. Power characteristics of inductive interconnect
    1307 -- 1320Emad Gad, Michel S. Nakhla. Efficient simulation of nonuniform transmission lines using integrated congruence transform
    1321 -- 1329A. Maheshwari, W. Burleson. Differential current-sensing for on-chip interconnects
    1330 -- 1347Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand. Interpretation of rent s rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models
    1348 -- 1359Maged Ghoneima, Yehea I. Ismail. Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses
    1360 -- 1370Sanjukta Bhanja, N. Ranganathan. Cascaded Bayesian inferencing for switching activity estimation with correlated inputs
    1371 -- 1374William N. N. Hung, Xiaoyu Song, T. Kam, Lerong Cheng, Guowu Yang. Routability checking for three-dimensional architectures
    1374 -- 1377Mauro Olivieri, Francesco Pappalardo 0002, Giuseppe Visalli. Bus-switch coding for reducing power dissipation in off-chip buses
    1377 -- 1381Chua-Chin Wang, Yih-Long Tseng, Hsien-Chih She, Ron Hu. A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications
    1381 -- 1385Myungchul Yoon. Sequence-switch coding for low-power data transmission
    1385 -- 1388Irith Pomeranz, Yervant Zorian. Fault isolation for nonisolated blocks

    Volume 12, Issue 11

    1132 -- 1147Jeong-Taek Kong. CAD for nanometer silicon design challenges and success
    1148 -- 1155Andrey V. Mezhiba, Eby G. Friedman. Impedance characteristics of power distribution grids in nanoscale integrated circuits
    1156 -- 1166Alexandre Schmid, Yusuf Leblebici. Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors
    1167 -- 1173Luigi Fortuna, Manuela La Rosa, Donata Nicolosi, Domenico Porto. Nanoscale system dynamical behaviors: from quantum-dot-based cell to 1-D arrays
    1174 -- 1181E. Y. Chou, J. C. Huang, M. S. Huang, M. C. Hsieh, A. Y. Hsu. Baud-rate channel equalization in nanometer technologies
    1182 -- 1191J.-L. Lai, P. C.-Y. Wu. Architectural design and analysis of learnable self-feedback ratio-memory cellular nonlinear network (SRMCNN) for nanoelectronic systems
    1192 -- 1200Hong-Yi Huang, Shih-Lun Chen. Interconnect accelerating techniques for sub-100-nm gigascale systems
    1201 -- 1208Garrett S. Rose, Matthew M. Ziegler, Mircea R. Stan. Large-signal two-terminal device model for nanoelectronic circuit analysis
    1209 -- 1213Chaohong Hu, Sorin Cotofana, Jianfei Jiang, Qiyu Cai. Analog-to-digital converter based on single-electron tunneling transistors
    1214 -- 1220C. Dwyer, L. Vicci, J. Poulton, D. Erie, Richard Superfine, Sean Washburn, Russell M. Taylor II. The design of DNA self-assembled computing circuitry
    1221 -- 1233Yuh-Fang Tsai, D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin. Characterization and modeling of run-time techniques for leakage power reduction
    1234 -- 1243Kartik Mohanram, Nur A. Touba. Lowering power consumption in concurrent checkers via input ordering
    1244 -- 1248Ramamurti Chandramouli, Vamsi K. Srikantam. Multimode power modeling and maximum-likelihood estimation
    1248 -- 1253Antonio Blotti, Roberto Saletti. Ultralow-power adiabatic circuit semi-custom design
    1253 -- 1257Gerald Esch Jr., Tom Chen. Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations

    Volume 12, Issue 10

    1004 -- 1014Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska. Individual wire-length prediction with application to timing-driven placement
    1015 -- 1027Jason Helge Anderson, Farid N. Najm. Power estimation techniques for FPGAs
    1028 -- 1037Chao-Yang Yeh, Malgorzata Marek-Sadowska. Sequential delay budgeting with interconnect prediction
    1038 -- 1050André DeHon, Raphael Rubin. Design of FPGA interconnect for multilevel metallization
    1051 -- 1065André DeHon. Unifying mesh- and tree-based programmable interconnect
    1066 -- 1075Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava. Empirical models for net-length probability distribution and applications
    1076 -- 1080Ketan N. Patel, Igor L. Markov. Error-correction and crosstalk avoidance in DSM busses
    1081 -- 1093Payam Heydari, Ravindran Mohanavelu. Design of ultrahigh-speed low-voltage CMOS CML buffers and latches
    1094 -- 1107Massimo Alioto, Gaetano Palumbo, Massimo Poli. Evaluation of energy consumption in RC ladder circuits driven by a ramp input
    1108 -- 1112Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand. Assessment of on-chip wire-length distribution models
    1113 -- 1118R. H. Turner, R. F. Woods. Highly efficient, limited range multipliers for LUT-based FPGA architectures
    1118 -- 1123Stelian Alupoaei, Srinivas Katkoori. Ant colony system application to macrocell overlap removal
    1123 -- 1126Tali Moreshet, R. Iris Bahar. Effects of speculation on performance and issue queue design
    1126 -- 1126Mohammad Maymandi-Nejad, Manoj Sachdev. Correction to A Digitally Programmable Delay Element: Design and Analysis

    Volume 12, Issue 1

    1 -- 11N. Ranganathan. Editorial
    12 -- 27Baris Taskin, Ivan S. Kourtev. Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits
    28 -- 41Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang. Timing modeling and optimization under the transmission line model
    42 -- 51Ankur Srivastava, Ryan Kastner, Chunhong Chen, Majid Sarrafzadeh. Timing driven gate duplication
    52 -- 66R. Galli, Alexandre F. Tenca. A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm
    67 -- 78Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Ivan S. Kourtev, Eby G. Friedman. Substrate coupling in digital circuits in mixed-signal smart-power systems
    79 -- 95Antonio H. Chan, Gordon W. Roberts. A jitter characterization system using a component-invariant Vernier delay line
    96 -- 107Tajana Simunic, Stephen P. Boyd, Peter W. Glynn. Managing power consumption in networks on chips
    108 -- 119Girish Varatkar, Radu Marculescu. On-chip traffic modeling and synthesis for MPEG-2 video applications
    120 -- 122Roman L. Lysecky, Susan Cotterell, Frank Vahid. A fast on-chip profiler memory using a pipelined binary tree
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