| 337 | -- | 338 | Jeff Alan Davis. Guest Editorial |
| 339 | -- | 348 | Joni Dambre, Dirk Stroobandt, Jan Van Campenhout. Toward the accurate prediction of placement wire length distributions in VLSI circuits |
| 349 | -- | 358 | Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni. An electromigration and thermal model of power wires for a priori high-level reliability prediction |
| 359 | -- | 366 | Shamik Das, Anantha Chandrakasan, Rafael Reif. Calibration of Rent s rule models for three-dimensional integrated circuits |
| 367 | -- | 372 | James W. Joyner, Payman Zarkesh-Ha, James D. Meindl. Global interconnect design in a three-dimensional system-on-a-chip |
| 373 | -- | 380 | Suhrid A. Wadekar, Alice C. Parker. Interconnect-based system-level energy and power prediction to guide architecture exploration |
| 381 | -- | 385 | PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia. On metrics for comparing interconnect estimation methods for FPGAs |
| 386 | -- | 394 | Andrey V. Mezhiba, Eby G. Friedman. Scaling trends of on-chip power distribution noise |
| 395 | -- | 407 | Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim. Analytical models and algorithms for the efficient signal integrity verification of inductance-effect-prominent multicoupled VLSI circuit interconnects |
| 408 | -- | 419 | Iouliia Skliarova, António de Brito Ferrari. A software/reconfigurable hardware SAT solver |
| 420 | -- | 436 | Khaled Benkrid, Danny Crookes. From application descriptions to hardware in seconds: a logic-based approach to bridging the gap |
| 437 | -- | 447 | Shizhong Mei, Yehea I. Ismail. Modeling skin and proximity effects with reduced realizable RL circuits |