| 885 | -- | 894 | Rouwaida Kanj, Elyse Rosenbaum. Critical evaluation of SOI design guidelines |
| 895 | -- | 900 | Chua-Chin Wang, Yih-Long Tseng, Hsien-Chih She, Chih-Chen Li, Ron Hu. A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula |
| 901 | -- | 909 | Chua-Chin Wang, Yih-Long Tseng, Hon-Yuan Leo, Ron Hu. A 4-kB 500-MHz 4-T CMOS SRAM using low-V::THN:: bitline drivers and high-V::THP:: latches |
| 910 | -- | 925 | Li Ding 0002, Pinaki Mazumder. On circuit techniques to improve noise immunity of CMOS dynamic logic |
| 926 | -- | 936 | Sarvesh H. Kulkarni, Dennis Sylvester. High performance level conversion for dual V::DD:: design |
| 937 | -- | 946 | Changbo Long, Lei He. Distributed sleep transistor network for power reduction |
| 947 | -- | 956 | L. T. Clark, M. Morrow, W. Brown. Reverse-body bias and supply collapse for low effective standby power |
| 957 | -- | 967 | Xinmiao Zhang, Keshab K. Parhi. High-speed VLSI architectures for the AES algorithm |
| 968 | -- | 977 | J. Kaza, C. Chakrabarti. Design and implementation of low-energy turbo decoders |
| 978 | -- | 994 | Mathew A. Sacker, Andrew D. Brown, Andrew J. Rushton, Peter R. Wilson. A behavioral synthesis system for asynchronous circuits |
| 995 | -- | 999 | Stefania Perri, Pasquale Corsonello, Maria Antonia Iachino, Marco Lanuzza, Giuseppe Cocorullo. Variable precision arithmetic circuits for FPGA-based multimedia processors |