| 249 | -- | 261 | Niraj K. Jha. Editorial |
| 262 | -- | 275 | Alexandru Andrei, Petru Eles, Zebo Peng, Marcus T. Schmitz, Bashir M. Al-Hashimi. Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection |
| 276 | -- | 285 | Nikhil Jayakumar, Sunil P. Khatri. A Predictably Low-Leakage ASIC Design Style |
| 286 | -- | 295 | Abbes Amira, Shrutisagar Chandrasekaran. Power Modeling and Efficient FPGA Implementation of FHT for Signal Processing |
| 296 | -- | 308 | Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems |
| 309 | -- | 318 | Warren J. Gross, Frank R. Kschischang, P. Glenn Gulak. Architecture and Implementation of an Interpolation Processor for Soft-Decision Reed-Solomon Decoding |
| 319 | -- | 327 | Ada S. Y. Poon. An Energy-Efficient Reconfigurable Baseband Processor for Wireless Communications |
| 328 | -- | 337 | Sizhong Chen, Tong Zhang, Yan Xin. Relaxed K-Best MIMO Signal Detector Design and VLSI Implementation |
| 338 | -- | 345 | Peiyi Zhao, Jason McNeely, Pradeep Golconda, Magdy A. Bayoumi, Robert A. Barcenas, Weidong Kuang. Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop |
| 346 | -- | 357 | Chen Shoushun, Amine Bermak. Arbitrated Time-to-First Spike CMOS Image Sensor With On-Chip Histogram Equalization |
| 358 | -- | 365 | Wei-Zen Chen, Da-Shin Lin. A 90-dB Omega 10-Gb/s Optical Receiver Analog Front-End in a 0.18µm CMOS Technology |
| 366 | -- | 376 | Justin Gregg, Tom W. Chen. Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing |