| 853 | -- | 854 | . Guest Editorial System-Level Interconnect Prediction |
| 855 | -- | 868 | Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li-Shiuan Peh. Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks |
| 869 | -- | 880 | Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo. Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors |
| 881 | -- | 894 | Jongsun Kim, Ingrid Verbauwhede, M.-C. Frank Chang. Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication |
| 895 | -- | 903 | Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown. Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow |
| 904 | -- | 912 | Andrew B. Kahng, Bao Liu, Qinke Wang. Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement |
| 913 | -- | 926 | Xiaoji Ye, Frank Liu, Peng Li. Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models |
| 927 | -- | 940 | Ian O Connor, Faress Tissafi-Drissi, Frédéric Gaffiot, Joni Dambre, Michiel De Wilde, Jan Van Campenhout, D. Van Thourhout, Dirk Stroobandt. Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect |
| 941 | -- | 944 | Jin Guo, Antonis Papanikolaou, H. Zhang, Francky Catthoor. Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture |
| 945 | -- | 948 | Wenyi Feng, Jonathan W. Greene. Post-Placement Interconnect Entropy |
| 948 | -- | 951 | Manuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, Paul Chow. Routability of Network Topologies in FPGAs |
| 952 | -- | 962 | Ray C. C. Cheung, Dong-U Lee, Wayne Luk, John D. Villasenor. Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method |
| 963 | -- | 970 | Ja Chun Ku, Yehea I. Ismail. Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits |
| 971 | -- | 975 | Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis. Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip |
| 975 | -- | 980 | Yuan Xie, Wayne Wolf, Haris Lekatsas. Code Decompression Unit Design for VLIW Embedded Processors |