| 493 | -- | 494 | Dimitris Gizopoulos, Robert C. Aitken, S. Kundu. Guest Editorial: Special Section on Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems |
| 495 | -- | 504 | Todd J. Foster, Dennis L. Lastor, Padmaraj Singh. First Silicon Functional Validation and Debug of Multicore Microprocessors |
| 505 | -- | 517 | Chung-Ho Chen, Chih-Kai Wei, Tai-Hua Lu, Hsun-Wei Gao. Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores |
| 518 | -- | 530 | Loganathan Lingappan, Niraj K. Jha. Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors |
| 531 | -- | 540 | Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra. Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit |
| 541 | -- | 545 | Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu. STEAC: A Platform for Automatic SOC Test Integration |
| 546 | -- | 559 | Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. Architectural Support for Run-Time Validation of Program Data Properties |
| 560 | -- | 571 | Mohamed Elgebaly, Manoj Sachdev. Variation-Aware Adaptive Voltage Scaling System |
| 572 | -- | 577 | Antonio Zenteno Ramirez, Guillermo Espinosa, Víctor H. Champac. Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops |
| 578 | -- | 591 | Encarnación Castillo, Uwe Meyer-Bäse, Antonio García, Luis Parrilla, Antonio Lloris-Ruíz. IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores |
| 592 | -- | 604 | Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail. Thermal Management of On-Chip Caches Through Power Density Minimization |
| 605 | -- | 609 | Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha. Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution |