| 613 | -- | 623 | Kanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown. Parametric Yield Analysis and Optimization in Leakage Dominated Technologies |
| 624 | -- | 636 | Tianpei Zhang, Sachin S. Sapatnekar. Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing |
| 637 | -- | 648 | J. C. Chi, H. H. Lee, S. H. Tsai, M. C. Chi. Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint |
| 649 | -- | 659 | H. Yamamoto, J. A. Davis. Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation |
| 660 | -- | 671 | Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy. Device-Aware Yield-Centric Dual-V::t:: Design Under Parameter Variations in Nanoscale Technologies |
| 672 | -- | 683 | Scott C. Smith. Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits |
| 684 | -- | 698 | Montek Singh, Steven M. Nowick. MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines |
| 699 | -- | 710 | Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar. Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC |
| 711 | -- | 715 | Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos. Sorter Based Permutation Units for Media-Enhanced Microprocessors |
| 716 | -- | 720 | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization |
| 720 | -- | 724 | Delong Shang, Alexandre Yakovlev, Albert Koelmans, Danil Sokolov, Alexandre V. Bystrov. Registers for Phase Difference Based Logic |
| 725 | -- | 728 | Shih-Chang Hsia, Szu-Hong Wang. Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform |