| 941 | -- | 951 | Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta. Satisfiability Models for Maximum Transition Power |
| 952 | -- | 964 | Han-Lin Li, Chia-Lin Yang, Hung-Wei Tseng. Energy-Aware Flash Memory Management in Virtual Memory System |
| 965 | -- | 974 | Yen-Jen Chang, Yuan-Hong Liao. Hybrid-Type CAM Design for Both Power and Performance Efficiency |
| 975 | -- | 984 | Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow. A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing |
| 985 | -- | 998 | Daler N. Rakhmatov. Energy Budget Approximations for Battery-Powered Systems With a Fixed Schedule of Active Intervals |
| 999 | -- | 1008 | Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis. Cost-Efficient SHA Hardware Accelerators |
| 1009 | -- | 1020 | Lei Wang, Niral Patel. Improving Error Tolerance for Multithreaded Register Files |
| 1021 | -- | 1034 | Zhonghai Lu, Axel Jantsch. TDM Virtual-Circuit Configuration for Network-on-Chip |
| 1035 | -- | 1045 | Pallav Gupta, Rui Zhang, Niraj K. Jha. Automatic Test Generation for Combinational Threshold Logic Networks |
| 1046 | -- | 1057 | Dan Zhao, Yi Wang. MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip |
| 1058 | -- | 1071 | Chin-Teng Lin, Yuan-Chu Yu, Lan-Da Van. Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor |
| 1072 | -- | 1082 | Chung-Ming Chen, Chung-Ho Chen. Configurable VLSI Architecture for Deblocking Filter in H.264/AVC |
| 1083 | -- | 1090 | Joshua Noseworthy, Miriam Leeser. Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA |
| 1091 | -- | 1096 | Miriam J. Akl, Magdy A. Bayoumi. Transition Skew Coding for Global On-Chip Interconnect |
| 1096 | -- | 1100 | S. Kwok, E. Y. Lam. Effective Uses of FPGAs for Brute-Force Attack on RC4 Ciphers |