| 609 | -- | 610 | Diana Marculescu, Jörg Henkel. Guest Editorial Special Section on Low-Power Electronics and Design |
| 611 | -- | 619 | Dongsheng Ma, Feng Luo. Robust Multiple-Phase Switched-Capacitor DC-DC Power Converter With Digital Interleaving Regulation Scheme |
| 620 | -- | 627 | Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto. Novel Video Memory Reduces 45 of Bitline Power Using Majority Logic and Data-Bit Reordering |
| 628 | -- | 638 | Elham Safi, Andreas Moshovos, Andreas G. Veneris. L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture |
| 639 | -- | 649 | Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers |
| 650 | -- | 661 | Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose. Selective Writeback: Reducing Register File Pressure and Energy Consumption |
| 662 | -- | 672 | Wonbok Lee, Kimish Patel, Massoud Pedram. GOP-Level Dynamic Thermal Management in MPEG-2 Decoding |
| 673 | -- | 677 | Prashant Singh, Jae-sun Seo, David Blaauw, Dennis Sylvester. Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect |
| 677 | -- | 682 | Jianwei Zhang, Yizheng Ye, Bin-Da Liu. A Current-Recycling Technique for Shadow-Match-Line Sensing in Content-Addressable Memories |
| 683 | -- | 692 | Azadeh Davoodi, Ankur Srivastava. Variability Driven Gate Sizing for Binning Yield Optimization |
| 693 | -- | 706 | Juan Carlos Baraza, Joaquin Gracia, Sara Blanc, Daniel Gil, Pedro J. Gil. Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code |
| 707 | -- | 713 | Rohit Singhal, Gwan Choi, Rabi N. Mahapatra. Data Handling Limits of On-Chip Interconnects |
| 714 | -- | 724 | Chong Zhao, Yi Zhao, Sujit Dey. Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits |
| 725 | -- | 732 | Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev, Stamatis Vassiliadis. Test Set Development for Cache Memory in Modern Microprocessors |
| 733 | -- | 744 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung. Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices |
| 745 | -- | 754 | Kaveh Shakeri, James D. Meindl. Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method |
| 755 | -- | 765 | Ying-Yen Chen, Jing-Jia Liou. Diagnosis Framework for Locating Failed Segments of Path Delay Faults |
| 766 | -- | 770 | Sampo Tuuna, Li-Rong Zheng, Jouni Isoaho, Hannu Tenhunen. Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid |
| 770 | -- | 774 | Shizhong Mei. Timing Jitter and Power Spectral Density of Random Walk Noise in VCO |
| 774 | -- | 779 | Mohamed Anane, Hamid Bessalah, Mohamed Issad, Nadjia Anane, Hassen Salhi. Higher Radix and Redundancy Factor for Floating Point SRT Division |