| 493 | -- | 503 | Katherine Compton, Scott Hauck. Automatic Design of Reconfigurable Domain-Specific Flexible Cores |
| 504 | -- | 516 | Heng Tan, Ronald F. DeMara. A Multilayer Framework Supporting Autonomous Run-Time Partial Reconfiguration |
| 517 | -- | 527 | Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel. A Compact and Accurate Gaussian Variate Generator |
| 528 | -- | 541 | Sanjukta Bhanja, Sudeep Sarkar. Thermal Switching Error Versus Delay Tradeoffs in Clocked QCA Circuits |
| 542 | -- | 553 | Daniele Rossi, André K. Nieuwland, Steven V. E. S. van Dijk, Richard P. Kleihorst, Cecilia Metra. Power Consumption of Fault Tolerant Busses |
| 554 | -- | 564 | Banit Agrawal, Timothy Sherwood. Ternary CAM Power and Delay Model: Extensions and Uses |
| 565 | -- | 578 | Yongmei Dai, Zhiyuan Yan, Ning Chen. Optimal Overlapped Message Passing Decoding of Quasi-Cyclic LDPC Codes |
| 579 | -- | 588 | Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton. Practical Asynchronous Interconnect Network Design |
| 589 | -- | 593 | Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen. Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime |
| 594 | -- | 598 | Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng. A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic |
| 598 | -- | 602 | John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim. Stack Sizing for Optimal Current Drivability in Subthreshold Circuits |
| 603 | -- | 608 | Zhenyu Gu, Changyun Zhu, Li Shang, Robert P. Dick. Application-Specific MPSoC Reliability Optimization |