| 1257 | -- | 1258 | Paolo Ienne, P. Petrov. Guest Editorial Special Section on Application Specific Processors |
| 1259 | -- | 1267 | Paolo Bonzini, Laura Pozzi. Recurrence-Aware Instruction Set Selection for Extensible Embedded Processors |
| 1268 | -- | 1280 | Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung. Outer Loop Pipelining for Application Specific Datapaths in FPGAs |
| 1281 | -- | 1294 | Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, Heinrich Meyr, Gerd Ascheid. A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors |
| 1295 | -- | 1308 | Lars Bauer, Muhammad Shafique, Jörg Henkel. Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation |
| 1309 | -- | 1320 | Timo Vogt, Norbert Wehn. A Reconfigurable ASIP for Convolutional and Turbo Decoding in an SDR Environment |
| 1321 | -- | 1334 | P. Dang. High Performance Architecture of an Application Specific Processor for the H.264 Deblocking Filter |
| 1335 | -- | 1345 | Rainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf. A Processing Path Dispatcher in Network Processor MPSoCs |
| 1346 | -- | 1357 | Hong Lu, A. Forin. Automatic Processor Customization for Zero-Overhead Online Software Verification |
| 1358 | -- | 1371 | Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu. Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel |
| 1372 | -- | 1384 | Saihua Lin, Huazhong Yang, Rong Luo. A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems |
| 1385 | -- | 1398 | Bing-Fei Wu, Hsin-Yuan Peng, Tung-Lung Yu. Efficient Hierarchical Motion Estimation Algorithm and Its VLSI Architecture |
| 1399 | -- | 1412 | Girish Varatkar, Naresh R. Shanbhag. Error-Resilient Motion Estimation Architecture |
| 1413 | -- | 1426 | Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey. Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication |