Journal: IEEE Trans. VLSI Syst.

Volume 16, Issue 9

1101 -- 1113Yu Wang, Ku He, Rong Luo, Hui Wang, Huazhong Yang. Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits
1114 -- 1126Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry. A Comparative Study Between Static and Dynamic Sleep Signal Generation Techniques for Leakage Tolerant Designs
1127 -- 1140Ayse Kivilcim Coskun, T. T. Rosing, Keith Whisnant, Kenny C. Gross. Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs
1141 -- 1150Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien. Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing
1151 -- 1161Ming-Der Shieh, Jun-Hong Chen, Hao-Hsuan Wu, Wen-Ching Lin. A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem
1162 -- 1175Kimmo U. Järvinen, Jorma Skyttä. On Parallelization of High-Speed Processors for Elliptic Curve Cryptography
1176 -- 1186Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla. A Trace-Based Framework for Verifiable GALS Composition of IPs
1187 -- 1198Takefumi Yoshikawa, Takashi Hirata, Tsuyoshi Ebuchi, Toru Iwata, Yukio Arima, Hiroyuki Yamauchi. An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics
1199 -- 1209Praveen Bhojwani, Rabi N. Mahapatra. Robust Concurrent Online Testing of Network-on-Chip-Based SoCs
1210 -- 1219Sándor P. Fekete, Jan van der Veen, Ali Ahmadinia, Diana Göhringer, Mateusz Majer, Jürgen Teich. Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device
1220 -- 1229A. Kapoor, Nikhil Jayakumar, Sunil P. Khatri. Dynamically De-Skewable Clock Distribution Methodology
1230 -- 1239Charbel J. Akl, Magdy A. Bayoumi. Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion
1240 -- 1243Dongsheng Ma, J. Wang, Minkyu Song. Adaptive On-Chip Power Supply With Robust One-Cycle Control Technique
1243 -- 1248A. Elyada, Ran Ginosar, U. Weiser. Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors
1248 -- 1251Ioannis Voyiatzis. An Accumulator-Based Compaction Scheme For Online BIST of RAMs
1251 -- 1256Lin Zhang, A. Carpenter, B. Ciftcioglu, A. Garg, M. Huang, Hui Wu. Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors