| 349 | -- | 368 | Yehea I. Ismail. Editorial |
| 369 | -- | 382 | Kenneth S. Stevens, Pankaj Golani, Peter A. Beerel. Energy and Performance Models for Synchronous and Asynchronous Communication |
| 383 | -- | 396 | Kevin Brownell, Ali Durlov Khan, Gu-Yeon Wei, David Brooks. Automating Design of Voltage Interpolation to Address Process Variations |
| 397 | -- | 410 | Stojan Z. Denic, Bane V. Vasic, Charalambos D. Charalambous, Jifeng Chen, Janet Meiling Wang. Information Theoretic Modeling and Analysis for Global Interconnects With Process Variations |
| 411 | -- | 419 | Xiaoke Qin, Chetan Muthry, Prabhat Mishra. Decoding-Aware Compression of FPGA Bitstreams |
| 420 | -- | 428 | Costas Argyrides, Dhiraj K. Pradhan, Taskin Koçak. Matrix Codes for Reliable and Cost Efficient Memory Chips |
| 429 | -- | 442 | Sotirios Xydis, George Economakos, Dimitrios Soudris, Kiamal Z. Pekmestzi. High Performance and Area Efficient Flexible DSP Datapath Synthesis |
| 443 | -- | 456 | Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack. FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis |
| 457 | -- | 468 | Aida Todri, Malgorzata Marek-Sadowska. Reliability Analysis and Optimization of Power-Gated ICs |
| 469 | -- | 482 | Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits |
| 483 | -- | 493 | Wei Xu, Hongbin Sun, XiaoBin Wang, Yiran Chen, Tong Zhang. Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM) |
| 494 | -- | 498 | Yongho Lee, Deog Kyoon Jeong, Taewhan Kim. Comprehensive Analysis and Control of Design Parameters for Power Gated Circuits |
| 499 | -- | 503 | Adam B. Kinsman, Nicola Nicolici. A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding |
| 503 | -- | 507 | Sheng-Chuan Liang, Hao-Chiao Hong. A Digitally Testable Sigma -Delta Modulator Using the Decorrelating Design-for-Digital-Testability |
| 508 | -- | 512 | Yiyu Shi, Jinjun Xiong, Howard Chen, Lei He. Runtime Resonance Noise Reduction with Current Prediction Enabled Frequency Actuator |
| 512 | -- | 516 | Francisco J. Jaime, M. A. Sánchez, Javier Hormigo, Julio Villalba, Emilio L. Zapata. High-Speed Algorithms and Architectures for Range Reduction Computation |
| 516 | -- | 520 | Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee. Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores |
| 520 | -- | 524 | Ling Zhang, Yulei Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng. On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals |