| 2141 | -- | 2148 | Ajay Taparia, Bhaskar Banerjee, Thayamkulangara R. Viswanathan. CS-CMOS: A Low-Noise Logic Family for Mixed Signal SoCs |
| 2149 | -- | 2157 | Jian-Wen Chen, Ruo He Yao, Wei Jing Wu. n+1 Multipliers |
| 2158 | -- | 2169 | Jin-Fu Lin, Soon-Jyh Chang, Te-Chieh Kung, Hsin-Wen Ting, Chih-Hao Huang. Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction |
| 2170 | -- | 2183 | Mango Chia-Tso Chao, Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang. A Novel Test Flow for One-Time-Programming Applications of NROM Technology |
| 2184 | -- | 2194 | Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Kun-Lun Luo, Wen Ching Wu. A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories |
| 2195 | -- | 2208 | Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton. Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs) |
| 2209 | -- | 2220 | Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman. Gate Leakage Impact on Full Open Defects in Interconnect Lines |
| 2221 | -- | 2228 | Seok Jae Lee, Ji-Woong Choi, Seon Wook Kim, Jongsun Park. A Reconfigurable FIR Filter Architecture to Trade Off Filter Performance for Dynamic Power Consumption |
| 2229 | -- | 2242 | Joydip Das, Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk. An Analytical Model Relating FPGA Architecture to Logic Density and Depth |
| 2243 | -- | 2255 | Aida Todri, Malgorzata Marek-Sadowska. Power Delivery for Multicore Systems |
| 2256 | -- | 2266 | Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman. Clock Distribution Networks in 3-D Integrated Systems |
| 2267 | -- | 2275 | Bharadwaj Amrutur, Pratap Kumar Das, Rajath Vasudevamurthy. 0.84 ps Resolution Clock Skew Measurement via Subsampling |
| 2276 | -- | 2289 | Zyad Hassan, Nicholas Allec, Fan Yang, Li Shang, Robert P. Dick, Xuan Zeng. Full-Spectrum Spatial-Temporal Dynamic Thermal Analysis for Nanometer-Scale Integrated Circuits |
| 2290 | -- | 2302 | Pei-Yun Tsai, Chung-Yi Lin. A Generalized Conflict-Free Memory Addressing Scheme for Continuous-Flow Parallel-Processing FFT Processors With Rescheduling |
| 2303 | -- | 2316 | Houman Homayoun, Avesta Sasan, Alexander V. Veidenbaum, Hsin-Cheng Yao, Shahin Golshan, Payam Heydari. MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits |
| 2317 | -- | 2321 | Sun-Mi Park, Ku-Young Chang. m) |
| 2322 | -- | 2325 | Martin Omaña, Cecilia Metra, T. M. Mak, Simon Tam. Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors |
| 2326 | -- | 2330 | Roberto Gutierrez, Javier Valls. Low Cost Hardware Implementation of Logarithm Approximation |
| 2330 | -- | 2335 | Xrysovalantis Kavousianos, Vasileios Tenentes, Krishnendu Chakrabarty, Emmanouil Kalligeros. Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets |
| 2335 | -- | 2338 | Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Bhargab B. Bhattacharya, Saraju P. Mohanty. A Routing-Aware ILS Design Technique |
| 2339 | -- | 2342 | David Kidd, Keven Dunn, Steve Nishimoto, Lief O'Donnell, D. Rodriguez. High Productivity Circuit Methodology for a Semi-Custom Embedded Processor |