| 1937 | -- | 1948 | Chih-Rung Chen, Wei-Su Wong, Ching-Te Chiu. 2 Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction |
| 1949 | -- | 1959 | Juliana Gjanci, Masud H. Chowdhury. A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC) |
| 1960 | -- | 1968 | Ajay Taparia, Bhaskar Banerjee, Thayamkulangara R. Viswanathan. Power-Supply Noise Reduction Using Active Inductors in Mixed-Signal Systems |
| 1969 | -- | 1982 | Minjin Zhang, Huawei Li, Xiaowei Li 0001. Path Delay Test Generation Toward Activation of Worst Case Coupling Effects |
| 1983 | -- | 1995 | Tsu-Wei Tseng, Jin-Fu Li. A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy |
| 1996 | -- | 2009 | Chengmo Yang, Alex Orailoglu. Full Fault Resilience and Relaxed Synchronization Requirements at the Cache-Memory Interface |
| 2010 | -- | 2022 | Mehdi Modarressi, Arash Tavakkol, Hamid Sarbazi-Azad. Application-Aware Topology Reconfiguration for On-Chip Networks |
| 2023 | -- | 2032 | Sansiri Tanachutiwat, Ming Liu, Wei Wang 0003. FPGA Based on Integration of CMOS and RRAM |
| 2033 | -- | 2044 | Yee Jern Chong, Sri Parameswaran. Configurable Multimode Embedded Floating-Point Units for FPGAs |
| 2045 | -- | 2057 | Debora Matos, Caroline Concatto, Márcio Eduardo Kreutz, Fernanda Lima Kastensmidt, Luigi Carro, Altamiro Amadeu Susin. Reconfigurable Routers for Low Power and High Performance |
| 2058 | -- | 2066 | Kiichi Niitsu, Vishwesh V. Kulkarni, Shinmo Kang, Hiroki Ishikuro, Tadahiro Kuroda. A 14-GHz AC-Coupled Clock Distribution Scheme With Phase Averaging Technique Using Single LC-VCO and Distributed Phase Interpolators |
| 2067 | -- | 2080 | M. Paul, P. Petrov. Dynamically Adaptive I-Cache Partitioning for Energy-Efficient Embedded Multitasking |
| 2081 | -- | 2094 | Houman Homayoun, Avesta Sasan, Jean-Luc Gaudiot, Alexander V. Veidenbaum. Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management |
| 2095 | -- | 2108 | Jonathan Rosenfeld, Eby G. Friedman. Linear and Switch-Mode Conversion in 3-D Circuits |
| 2109 | -- | 2119 | Chao Lu, Chi-Ying Tsui, Wing-Hung Ki. Vibration Energy Scavenging System With Maximum Power Tracking for Micropower Applications |
| 2120 | -- | 2125 | Jiajing Wang, Benton H. Calhoun. Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations |
| 2125 | -- | 2129 | Arash Hariri, Arash Reyhani-Masoleh. Digit-Level Semi-Systolic and Systolic Structures for the Shifted Polynomial Basis Multiplication Over Binary Extension Fields |
| 2130 | -- | 2134 | Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry. A Bias-Dependent Model for the Impact of Process Variations on the SRAM Soft Error Immunity |
| 2135 | -- | 2139 | Frank P. Burns, Alexandre V. Bystrov, Albert Koelmans, Alexandre Yakovlev. Security Evaluation of Balanced 1-of- n Circuits |