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Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Suki Kim. A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology. IEEE Trans. VLSI Syst., 19(9):1718-1722, 2011. [doi]
Abstract is missing.