The following publications are possibly variants of this publication:
- A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS TechnologyWon-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Shin-Deok Kang, Ji-Yeon Yang, Hyeng-Ouk Lee, Dong Uk Lee, Sujeong Sim, Young-Ju Kim, Won Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyang-Hwa Choi, Hyung-Wook Moon, Seung-Wook Kwack, Jung Woo Lee, Young-Kyoung Choi, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Ye Seok Yang. isscc 2008: 282-283 [doi]
- A low-jitter mixed-mode DLL for high-speed DRAM applicationsJae-Joon Kim, Sang-Bo Lee, Tae-Sung Jung, Chang-Hyun Kim, Soo-In Cho, Beomsup Kim. jssc, 35(10):1430-1436, 2000. [doi]
- A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection schemeDongsuk Shin, Won-Joo Yun, Hyun-Woo Lee, Young-Jung Choi, Suki Kim, Chulwoo Kim. esscirc 2008: 82-85 [doi]
- A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLLKi Won Lee, Joo-Hwan Cho, Byoung Jin Choi, Geun-Il Lee, Ho-Don Jung, Woo-Young Lee, Ki-Chon Park, Yongsuk Joo, Jaehoon Cha, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn. jssc, 42(11):2369-2377, 2007. [doi]
- A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLLDong Uk Lee, Hyun-Woo Lee, Ki Chang Kwean, Young-Kyoung Choi, Hyong Uk Moon, Seung-Wook Kwack, Shin-Deok Kang, Kwan-Weon Kim, Yong-Ju Kim, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn, Joong Sik Kih. isscc 2006: 547-556 [doi]
- A DLL with Jitter-Reduction Techniques for DRAM InterfacesByung-Guk Kim, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Soo-In Cho. isscc 2007: 496-497 [doi]
- A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAMSe-jun Kim, Sang Hoon Hong, Jae-Kyung Wee, Joo-Hwan Cho, Pil Soo Lee, Jin-Hong Ahn, Jin-Yong Chung. jssc, 37(6):726-734, 2002. [doi]
- A portable digital DLL for high-speed CMOS interface circuitsBruno W. Garlepp, Kevin S. Donnelly, Jun Kim, Pak Shing Chau, Jared L. Zerbe, Charlie Huang, Chanh Tran, Clemenz L. Portmann, Donald Stark, Yiu-Fai Chan, Thomas H. Lee, Mark A. Horowitz. jssc, 34(5):632-644, 1999. [doi]
- A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM InterfacesByung-Guk Kim, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Soo-In Cho. jssc, 44(5):1522-1530, 2009. [doi]
- A low-power fast-lock DCC with a digital duty-cycle adjuster for LPDDR3 and LPDDR4 DRAMsJongsun Kim, S. W. Han. ieiceee, 15(7):20180156, 2018. [doi]
- A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOSHyun-Woo Lee, Won-Joo Yun, Young-Kyoung Choi, Hyang-Hwa Choi, Jong Jin Lee, Ki-Han Kim, Shin-Deok Kang, Ji-Yeon Yang, Jae-Suck Kang, Hyeng-Ouk Lee, Dong Uk Lee, Sujeong Sim, Young-Ju Kim, Won Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyung-Wook Moon, Seung-Wook Kwack, Jung Woo Lee, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung. isscc 2009: 140-141 [doi]