| 725 | -- | 736 | Massimo Alioto, Elio Consoli, Gaetano Palumbo. Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies |
| 737 | -- | 750 | Massimo Alioto, Elio Consoli, Gaetano Palumbo. Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit |
| 751 | -- | 762 | Massimo Alioto. Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET Standard Cells |
| 763 | -- | 773 | Hailong Jiao, Volkan Kursun. Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits |
| 774 | -- | 786 | Renatas Jakushokas, Eby G. Friedman. Multi-Layer Interdigitated Power Distribution Networks |
| 787 | -- | 795 | John Keane, S. Venkatraman, Paulo F. Butzen, Chris H. Kim. An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization |
| 796 | -- | 808 | Server Kasap, Khaled Benkrid. High Performance Phylogenetic Analysis With Maximum Parsimony on Reconfigurable Hardware |
| 809 | -- | 817 | Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay. A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective |
| 818 | -- | 831 | Woohyung Chun, Sungroh Yoon, Sangjin Hong. Energy-Aware Interconnect Resource Reduction Through Buffer Access Manipulation for Data-Centric Applications |
| 832 | -- | 845 | Jintae Kim, S. Limotyrakis, Chih-Kong Ken Yang. Multilevel Power Optimization of Pipelined A/D Converters |
| 846 | -- | 856 | Jingye Xu, Masud H. Chowdhury. Fast Waveform Estimation (FWE) for Timing Analysis |
| 857 | -- | 868 | Xin Chen, Jun Yang, Longxing Shi. A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique |
| 869 | -- | 882 | Rajiv V. Joshi, Rouwaida Kanj, V. Ramadurai. A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design |
| 883 | -- | 894 | Mohammad Sharifkhani, E. Rahiminejad, Shah M. Jahinuzzaman, Manoj Sachdev. A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs |
| 895 | -- | 899 | Markus Myllylä, Joseph R. Cavallaro, Markku J. Juntti. Architecture Design and Implementation of the Metric First List Sphere Detector Algorithm |
| 900 | -- | 904 | Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi. A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors |
| 904 | -- | 909 | Ren-Jie Lee, Hung-Ming Chen. Efficient Package Pin-Out Planning With System Interconnects Optimization for Package-Board Codesign |
| 909 | -- | 914 | Jiajing Wang, A. Hoefler, Benton H. Calhoun. An Enhanced Canary-Based System With BIST for SRAM Standby Power Reduction |
| 914 | -- | 918 | Peiyi Zhao, Jason McNeely, Weidong Kuang, Nan Wang, Zhongfeng Wang. Design of Sequential Elements for Low Power Clocking System |
| 918 | -- | 923 | Koustav Bhattacharya, N. Ranganathan. Placement for Immunity of Transient Faults in Cell-Based Design of Nanometer Circuits |