| 1125 | -- | 1135 | Hyun Choi, Alfred V. Gomes, Abhijit Chatterjee. Signal Acquisition of High-Speed Periodic Signals Using Incoherent Sub-Sampling and Back-End Signal Reconstruction Algorithms |
| 1136 | -- | 1146 | Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh. Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers |
| 1147 | -- | 1153 | Marco Bucci, Luca Giancane, Raimondo Luzzi, Giuseppe Scotti, Alessandro Trifiletti. Delay-Based Dual-Rail Precharge Logic |
| 1154 | -- | 1166 | Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin, James F. Buckwalter, Chung-Kuan Cheng. Prediction and Comparison of High-Performance On-Chip Global Interconnection |
| 1167 | -- | 1180 | Wei-Chih Hsieh, Wei Hwang. Adaptive Power Control Technique on Power-Gated Circuitries |
| 1181 | -- | 1191 | Akhilesh Kumar, Mohab Anis. IR-Drop Aware Clustering Technique for Robust Power Grid in FPGAs |
| 1192 | -- | 1204 | Hao-I Yang, Wei Hwang, Ching-Te Chuang. Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices |
| 1205 | -- | 1217 | Yamarita Villavicencio, Francesco Musolino, Franco Fiori. Electrical Model of Microcontrollers for the Prediction of Electromagnetic Emissions |
| 1218 | -- | 1228 | Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Hsiang Chen, Jen-Chieh Liu. A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit |
| 1229 | -- | 1238 | Xinmiao Zhang, Fang Cai. Reduced-Complexity Decoder Architecture for Non-Binary LDPC Codes |
| 1239 | -- | 1248 | Yasser Ismail, Mohsen Shaaban, Jason McNeely, Magdy A. Bayoumi. An Efficient Adaptive High Speed Manipulation Architecture for Fast Variable Padding Frequency Domain Motion Estimation |
| 1249 | -- | 1262 | Woohyung Chun, Sungroh Yoon, Sangjin Hong. Buffer Controller-Based Multiple Processing Element Utilization for Dataflow Synthesis |
| 1263 | -- | 1276 | Juan Antonio Clemente, Javier Resano, Carlos González, Daniel Mozos. A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems |
| 1277 | -- | 1290 | Shantanu Dutt, Huan Ren. Discretized Network Flow Techniques for Timing and Wire-Length Driven Incremental Placement With White-Space Satisfaction |
| 1291 | -- | 1304 | Huan Ren, Shantanu Dutt. A Provably High-Probability White-Space Satisfaction Algorithm With Good Performance for Standard-Cell Detailed Placement |
| 1305 | -- | 1309 | David C. W. Ng, David K. K. Kwong, Ngai Wong. A Sub-1 V, 26 muW, Low-Output-Impedance CMOS Bandgap Reference With a Low Dropout or Source Follower Mode |
| 1310 | -- | 1315 | I. Jung, D. Shin, T. Kim, C. Kim. A 140 Mb/s to 1.96 Gb/s Referenceless Transceiver With 7.2 mus Frequency Acquisition Time |
| 1315 | -- | 1319 | S. Lin, Y. B. Kim, F. Lombardi. Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS |
| 1319 | -- | 1323 | Hao Xu, Wen-Ben Jone, Ranga Vemuri. Aggressive Runtime Leakage Control Through Adaptive Light-Weight V::th:: Hopping With Temperature and Process Variation |