| 525 | -- | 537 | Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim. A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache |
| 538 | -- | 547 | Shoushun Chen, Amine Bermak, Yan Wang. A CMOS Image Sensor With On-Chip Image Compression Based on Predictive Boundary Adaptation and Memoryless QTD Algorithm |
| 548 | -- | 558 | Xuebin Wu, Zhiyuan Yan. Efficient CODEC Designs for Crosstalk Avoidance Codes Based on Numeral Systems |
| 559 | -- | 570 | Ehab Anis Daoud, Nicola Nicolici. Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation |
| 571 | -- | 584 | Fu-Ching Yang, Yi-Ting Lin, Chung-Fu Kao, Ing-Jer Huang. An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC |
| 585 | -- | 591 | Tsung-Hsien Lin, Chao-Ching Chi, Wei-Hao Chiu, Yu-Hsiang Huang. A Synchronous 50 Duty-Cycle Clock Generator in 0.35- μ m CMOS |
| 592 | -- | 602 | Shih-Yuan Kao, Shen-Iuan Liu. A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression |
| 603 | -- | 614 | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits |
| 615 | -- | 628 | Yu Wang 0002, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang. Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques |
| 629 | -- | 637 | Yuejian Wu, Sandy Thomson, Dale Mutcher, Eric Hall. Built-In Functional Tests for Silicon Validation and System Integration of Telecom SoC Designs |
| 638 | -- | 646 | Qiang Zhou, Jin Shi, Bin Liu 0007, Yici Cai. Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs |
| 647 | -- | 658 | Nauman H. Khan, Syed M. Alam, Soha Hassoun. Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies |
| 659 | -- | 667 | Chun-Yu Hsieh, Hong-Wei Huang, Ke-Horng Chen. A 1-V, 16.9 ppm/ ^{/circ} C, 250 nA Switched-Capacitor CMOS Voltage Reference |
| 668 | -- | 681 | Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt. A Multi-Granularity Power Modeling Methodology for Embedded Processors |
| 682 | -- | 695 | Chong-Fatt Law, Bah-Hwee Gwee, Joseph Sylvester Chang. Modeling and Synthesis of Asynchronous Pipelines |
| 696 | -- | 700 | Inwook Kong, Earl E. Swartzlander Jr.. A Goldschmidt Division Method With Faster Than Quadratic Convergence |
| 701 | -- | 705 | Jaehyouk Choi, Stephen T. Kim, Woonyun Kim, Kwan-Woo Kim, Kyutae Lim, Joy Laskar. A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor |
| 705 | -- | 709 | Hsieh-Hung Hsieh, Huan-Sheng Chen, Ping-Hsi Hung, Liang-Hung Lu. Experimental 5-GHz RF Frontends for Ultra-Low-Voltage and Ultra-Low-Power Operations |
| 709 | -- | 714 | Yuan-Ho Chen, Tsin-Yuan Chang, Chung-Yi Li. High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree |
| 714 | -- | 717 | Anita Kumari, Sanjukta Bhanja. Landauer Clocking for Magnetic Cellular Automata (MCA) Arrays |
| 718 | -- | 721 | Mariano Aguirre-Hernandez, Mónico Linares Aranda. CMOS Full-Adders for Energy-Efficient Arithmetic Applications |