| 925 | -- | 938 | H.-C. Kuo, L.-C. Wu, H.-T. Huang, S. T. Hsu, Y.-L. Lin. A Low-Power High-Performance H.264/AVC Intra-Frame Encoder for 1080pHD Video |
| 939 | -- | 952 | C.-W. Lin, M. C.-T. Chao, Y.-S. Huang. A Novel Pixel Design for AM-OLED Displays Using Nanocrystalline Silicon TFTs |
| 953 | -- | 962 | Arindam Basu, Paul E. Hasler. A Fully Integrated Architecture for Fast and Accurate Programming of Floating Gates Over Six Decades of Current |
| 963 | -- | 972 | Satendra Kumar Maurya, Lawrence T. Clark. A Dynamic Longest Prefix Matching Content Addressable Memory for IP Routing |
| 973 | -- | 986 | J. G. Mueller, Resve A. Saleh. Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die Variations |
| 987 | -- | 996 | Y. Ye, F. Liu, M. Chen, S. Nassif, Y. Cao. Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness |
| 997 | -- | 1010 | M. Wang, Z. Shao, J. Xue. On Reducing Hidden Redundant Memory Accesses for DSP Applications |
| 1011 | -- | 1022 | Jia Zhao, Sailaja Madduri, Ramakrishna Vadlamani, Wayne Burleson, Russell Tessier. A Dedicated Monitoring Infrastructure for Multicore Processors |
| 1023 | -- | 1033 | Saleh Abdel-Hafeez, Ann Gordon-Ross. A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic |
| 1034 | -- | 1047 | C. Kyrkou, Theocharis Theocharides. A Flexible Parallel Hardware Architecture for AdaBoost-Based Real-Time Object Detection |
| 1048 | -- | 1061 | Markus Koester, Wayne Luk, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert. Design Optimizations for Tiled Partially Reconfigurable Systems |
| 1062 | -- | 1074 | Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi. EGRA: A Coarse Grained Reconfigurable Architectural Template |
| 1075 | -- | 1085 | Jonathan Rosenfeld, Eby G. Friedman. A Distributed Filter Within a Switching Converter for Application to 3-D Integrated Circuits |
| 1086 | -- | 1089 | Muhammad E. S. Elrabaa. Robust Two-Phase RZ Asynchronous SoC Interconnects |
| 1090 | -- | 1094 | Dimitris Magos, Ioannis Voyiatzis, Steffen Tarnick. An Accumulator - Based Test-Per-Clock Scheme |
| 1094 | -- | 1098 | Irith Pomeranz, Sudhakar M. Reddy. On Functional Broadside Tests With Functional Propagation Conditions |
| 1099 | -- | 1103 | Sangmin Kim, Gerald E. Sobelman, Hanho Lee. A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes |
| 1104 | -- | 1108 | Irith Pomeranz, Sudhakar M. Reddy. Broadside and Functional Broadside Tests for Partial-Scan Circuits |
| 1108 | -- | 1112 | Irith Pomeranz, Sudhakar M. Reddy. Static Test Data Volume Reduction Using Complementation or Modulo- M Addition |
| 1113 | -- | 1117 | D. Sheng, C.-C. Chung, C.-Y. Lee. A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications |
| 1118 | -- | 1122 | Jing-hu Li, Xing-Bao Zhang, Ming-Yan Yu. A 1.2-V Piecewise Curvature-Corrected Bandgap Reference in 0.5 μ m CMOS Process |