| 1 | -- | 9 | Myint Wai Phyu, Kangkang Fu, Wang Ling Goh, Kiat Seng Yeo. Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops |
| 10 | -- | 23 | Alexandru Andrei, Petru Eles, Olivera Jovanovic, Marcus T. Schmitz, Jens Ogniewski, Zebo Peng. Quasi-Static Voltage Scaling for Energy Minimization With Time Constraints |
| 24 | -- | 32 | Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang. SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage |
| 33 | -- | 41 | Cheng-Hung Lin, Shih-Chieh Chang. Efficient Pattern Matching Algorithm for Memory Architecture |
| 42 | -- | 51 | Marco D. Santambrogio, Renato Stefanelli. A New Compact SD2 Positive Integer Triangular Array Division Circuit |
| 52 | -- | 60 | Jiun-Ping Wang, Shiann-Rong Kuang, Shish-Chang Liang. High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications |
| 61 | -- | 70 | Joonhee Lee, Sunghyun Park, SeongHwan Cho. A 470-µW 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider With an In-Phase Dual-Input Injection Scheme |
| 71 | -- | 84 | Ian Kuon, Jonathan Rose. Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design |
| 85 | -- | 91 | Mehran Mozaffari Kermani, Arash Reyhani-Masoleh. A Lightweight High-Performance Fault Detection Scheme for the Advanced Encryption Standard Using Composite Fields |
| 92 | -- | 103 | Shahin Nazarian, Hanif Fatemi, Massoud Pedram. Accurate Timing and Noise Analysis of Combinational and Sequential Logic Cells Using Current Source Modeling |
| 104 | -- | 117 | Jason Nemeth, Rui Min, Wen-Ben Jone, Yiming Hu. Location Cache Design and Performance Analysis for Chip Multiprocessors |
| 118 | -- | 129 | Chao Shi, Man Kay Law, Amine Bermak. A Novel Asynchronous Pixel for an Energy Harvesting CMOS Image Sensor |
| 130 | -- | 141 | Claude Thibeault, Yassine Hariri. CDelta IDDQ : Improving Current-Based Testing and Diagnosis Through Modified Test Pattern Generation |
| 142 | -- | 146 | Irith Pomeranz, Sudhakar M. Reddy. Fixed-State Tests for Delay Faults in Scan Designs |
| 146 | -- | 151 | Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating |
| 151 | -- | 156 | Sherif A. Tawfik, Volkan Kursun. Multi-Threshold Voltage FinFET Sequential Circuits |
| 156 | -- | 160 | Shau-Yu Cheng, Chueh-An Tsai, Terng-Yin Hsu. Channel Estimator and Aliasing Canceller for Equalizing and Decoding Non-Cyclic Prefixed Single-Carrier Block Transmission via MIMO-OFDM Modem |
| 161 | -- | 165 | Minki Cho, Jason Schlessman, Wayne Wolf, Saibal Mukhopadhyay. Reconfigurable SRAM Architecture With Spatial Voltage Scaling for Low Power Mobile Multimedia Applications |
| 165 | -- | 170 | Hsuan-Jung Hsu, Shi-Yu Huang. A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme |