| 173 | -- | 174 | N. K. Jha. Editorial Announcing a New Editor-in-Chief |
| 175 | -- | 181 | Tien-Yu Lo, Chung-Chih Hung. A 1 GHz Equiripple Low-Pass Filter With a High-Speed Automatic Tuning Scheme |
| 182 | -- | 195 | Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry. Analytical Soft Error Models Accounting for Die-to-Die and Within-Die Variations in Sub-Threshold SRAM Cells |
| 196 | -- | 204 | Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo, Jeremy Yung Shern Low. Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM |
| 205 | -- | 216 | Jongyoon Jung, Taewhan Kim. Scheduling and Resource Binding Algorithm Considering Timing Variation |
| 217 | -- | 226 | Hariharan Sankaran, Srinivas Katkoori. Simultaneous Scheduling, Allocation, Binding, Re-Ordering, and Encoding for Crosstalk Pattern Minimization During High-Level Synthesis |
| 227 | -- | 236 | Jun Seomun, Youngsoo Shin. Design and Optimization of Power-Gated Circuits With Autonomous Data Retention |
| 237 | -- | 249 | Hao Xu, Ranga Vemuri, Wen-Ben Jone. Dynamic Characteristics of Power Gating During Mode Transition |
| 250 | -- | 263 | Yao Guo, Pritish Narayanan, Mahmoud A. Bennaser, Saurabh Chheda, Csaba Andras Moritz. Energy-Efficient Hardware Data Prefetching |
| 264 | -- | 273 | Jae-sun Seo, Himanshu Kaul, Ram Krishnamurthy, Dennis Sylvester, David Blaauw. A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect |
| 274 | -- | 282 | Judith Liu-Jimenez, Raul Sánchez-Reillo, Belen Fernandez-Saavedra. Iris Biometrics for Embedded Systems |
| 283 | -- | 294 | Ping Chen, Andy Ye. The Effect of Multi-Bit Correlation on the Design of Field-Programmable Gate Array Routing Resources |
| 295 | -- | 304 | Rakesh Gnana David Jeyasingh, Navakanta Bhat, Bharadwaj S. Amrutur. Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique |
| 305 | -- | 318 | Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu. Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding |
| 319 | -- | 332 | Ramachandra Achar, Michel S. Nakhla, Harjot S. Dhindsa, Arvind R. Sridhar, Douglas Paul, Natalie Nakhla. Parallel and Scalable Transient Simulator for Power Grids via Waveform Relaxation (PTS-PWR) |
| 333 | -- | 337 | Irith Pomeranz, Sudhakar M. Reddy. Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits |
| 338 | -- | 341 | Shu-Yi Wong, Chunhong Chen, Q. M. Jonathan Wu. Low Power Chien Search for BCH Decoder Using RT-Level Power Management |
| 342 | -- | 346 | Sourajeet Roy, Anestis Dounavis. Efficient Delay and Crosstalk Modeling of RLC Interconnects Using Delay Algebraic Equations |