| 1965 | -- | 1974 | Thomas Plos, Michael Hutter, Martin Feldhofer, M. Stiglic, F. Cavaliere. Security-Enabled Near-Field Communication Tag With Flexible Architecture Supporting Asymmetric Cryptography |
| 1975 | -- | 1988 | Ajay N. Bhoj, Niraj K. Jha. Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology |
| 1989 | -- | 1998 | Saleh Abdel-Hafeez, Ann Gordon-Ross, B. Parhami. Scalable Digital CMOS Comparator Using a Parallel Prefix Tree |
| 1999 | -- | 2009 | Shiann-Rong Kuang, Jiun-Ping Wang, Kai-Cheng Chang, Huan-Wei Hsu. Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems |
| 2010 | -- | 2023 | Fang Cai, Xinmiao Zhang. Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes |
| 2024 | -- | 2033 | Nicolas Laflamme-Mayer, Walder Andre, Olivier Valorge, Yves Blaquière, M. Sawan. Configurable Input-Output Power Pad for Wafer-Scale Microelectronic Systems |
| 2034 | -- | 2044 | Vikram Chaturvedi, T. Anand, Bharadwaj Amrutur. An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording |
| 2045 | -- | 2054 | Bing Shi, Yufu Zhang, Ankur Srivastava. Dynamic Thermal Management Under Soft Thermal Constraints |
| 2055 | -- | 2068 | Chia-Chun Lin, A. Chakrabarti, N. K. Jha. Optimized Quantum Gate Library for Various Physical Machine Descriptions |
| 2069 | -- | 2079 | B. Mohammad, D. Homouz, H. Elgabra. Robust Hybrid Memristor-CMOS Memory: Modeling and Design |
| 2080 | -- | 2093 | Minyoung Song, Young-Ho Kwak, Sunghoon Ahn, Hojin Park, Chulwoo Kim. 10-315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation |
| 2094 | -- | 2105 | Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha. 3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits |
| 2106 | -- | 2117 | A. Kapoor, J. P. de Gyvez. Architectural Analysis for Wirelessly Powered Computing Platforms |
| 2118 | -- | 2131 | Chih-Hao Chao, Kun-Chih Chen, An-Yeu Wu. Routing-Based Traffic Migration and Buffer Allocation Schemes for 3-D Network-on-Chip Systems With Thermal Limit |
| 2132 | -- | 2140 | Hing-Kit Kwan, D. C. W. Ng, V. W. K. So. Design and Analysis of Dual-Mode Digital-Control Step-Up Switched-Capacitor Power Converter With Pulse-Skipping and Numerically Controlled Oscillator-Based Frequency Modulation |
| 2141 | -- | 2154 | Dominic DiTomaso, Randy Morris, Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri. Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips |
| 2155 | -- | 2159 | Jang-Woo Lee, Hong-Jung Kim, Chun-Seok Jeong, Jae-Jin Lee, Changsik Yoo. Skew Compensation Technique for Source-Synchronous Parallel DRAM Interface |
| 2160 | -- | 2164 | Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee. Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation |