Journal: IEEE Trans. VLSI Syst.

Volume 21, Issue 9

1573 -- 1582Guoqing Deng, Chunhong Chen. Binary Multiplication Using Hybrid MOS and Multi-Gate Single-Electron Transistors
1583 -- 1595Dongsoo Lee, Kaushik Roy. Area Efficient ROM-Embedded SRAM Cache
1596 -- 1607Chengwu Tao, Ayman A. Fayed. PWM Control Architecture With Constant Cycle Frequency Hopping and Phase Chopping for Spur-Free Operation in Buck Regulators
1608 -- 1618Jiann-Jong Chen, Ming-Xiang Lu, Tse-Hsu Wu, Yuh-Shyan Hwang. Sub-1-V Fast-Response Hysteresis-Controlled CMOS Buck Converter Using Adaptive Ramp Techniques
1619 -- 1631Kyu-Nam Shim, Jiang Hu. Boostable Repeater Design for Variation Resilience in VLSI Interconnects
1632 -- 1643Yoonmyung Lee, Daeyeon Kim, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, David Blaauw, Dennis Sylvester. Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs)
1644 -- 1654Won-Ho Park, Chih-Kong Ken Yang. Effects of Using Advanced Cooling Systems on the Overall Power Consumption of Processors
1655 -- 1668Yanheng Zhang, Chris Chu. RegularRoute: An Efficient Detailed Router Applying Regular Routing Patterns
1669 -- 1682Chun-Yi Lee, Niraj K. Jha. Variable-Pipeline-Stage Router
1683 -- 1692Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown. Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection
1693 -- 1704Kalarikkal Absel, Lijo Manuel, R. K. Kavitha. Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic
1705 -- 1714Irith Pomeranz. On Test Compaction of Broadside and Skewed-Load Test Cubes
1715 -- 1726Jaeyong Chung, Jacob A. Abraham. Concurrent Path Selection Algorithm in Statistical Timing Analysis
1727 -- 1737Chi-Ying Lee, Chih-Cheng Hsieh, Jenn-Chyou Bor. 2.4-GHz 10-Mb/s BFSK Embedded Transmitter With a Stacked-LC DCO for Wireless Testing Systems
1738 -- 1742Guoqing Deng, Chunhong Chen. A SET/MOS Hybrid Multiplier Using Frequency Synthesis
1742 -- 1747Chia-Min Chen, Tung-Wei Tsai, Chung-Chih Hung. Fast Transient Low-Dropout Voltage Regulator With Hybrid Dynamic Biasing Technique for SoC Application
1747 -- 1751Shaowei Zhen, Xiaohui Zhu, Ping Luo, Yajuan He, Bo Zhang. Digital Error Corrector for Phase Lead-Compensated Buck Converter in DVS Applications
1751 -- 1756Yanheng Zhang, Chris Chu. Fast and Effective Placement Refinement for Routability
1756 -- 1761Jun Lin, Zhiyuan Yan. Efficient Shuffled Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes
1762 -- 1766Samah Mohamed Saeed, Ozgur Sinanoglu, Sobeeh Almukhaizim. Predictive Techniques for Projecting Test Data Volume Compression

Volume 21, Issue 8

1377 -- 1387Ren-Jie Lee, Hsin-Wu Hsu, Hung-Ming Chen. Board- and Chip-Aware Package Wire Planning
1388 -- 1397Zhuo Feng. Scalable Multilevel Vectorless Power Grid Voltage Integrity Verification
1398 -- 1409Abdullah Nazma Nowroz, Gary Woods, Sherief Reda. Power Mapping of Integrated Circuits Using AC-Based Thermography
1410 -- 1420Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni. Nanomagnetic Logic Microprocessor: Hierarchical Power Model
1421 -- 1431Arun Palaniappan, Samuel Palermo. A Design Methodology for Power Efficiency Optimization of High-Speed Equalized-Electrical I/O Architectures
1432 -- 1446Jacob Postman, Tushar Krishna, Christopher Edmonds, Li-Shiuan Peh, Patrick Chiang. SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects
1447 -- 1453Hongyi Wang, Yanzhao Ma, Jun Cheng. Soft-Start Method With Small Capacitor Charged by Pulse Current and Gain-Degeneration Error Amplifier for On-Chip DC-DC Power Converters
1454 -- 1468Mojtaba Ebrahimi, Seyed Ghassem Miremadi, Hossein Asadi, Mahdi Fazeli. Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems
1469 -- 1480Minoo Mirsaeedi, Andres J. Torres, Mohab H. Anis. Litho-Friendly Decomposition Method for Self-Aligned Double Patterning
1481 -- 1495Ching-Te Chiu, Yu-Hao Hsu, Wei-Chih Lai, Jen-Ming Wu, Shawn S. H. Hsu, Yang-Syu Lin, Fanta Chen, Min-Sheng Kao, Yarsun Hsu. Low Propagation Delay Load-Balanced 4 $\, \times\, $4 Switch Fabric IC in 0.13-$\mu{\rm m}$ CMOS Technology
1496 -- 1505Richard B. Wunderlich, Farhan Adil, Paul E. Hasler. Floating Gate-Based Field Programmable Mixed-Signal Array
1506 -- 1515Yanjie Peng, Xinming Huang, Andrew G. Klein, Kai Zhang. Design and Implementation of a Low-Complexity Symbol Detector for Sparse Channels
1516 -- 1525Dandan Chen, Kiat Seng Yeo, Xiaomeng Shi, Manh Anh Do, Chirn Chye Boon, Wei Meng Lim. Cross-Coupled Current Conveyor Based CMOS Transimpedance Amplifier for Broadband Data Transmission
1526 -- 1539Zhuo Feng, Peng Li. Fast Thermal Analysis on GPU for 3D ICs With Integrated Microchannel Cooling
1540 -- 1544Li Li, Ken Choi, Haiqing Nan. Activity-Driven Fine-Grained Clock Gating and Run Time Power Gating Integration
1545 -- 1549Mohammad Esmaeildoust, Dimitrios Schinianakis, Hamid Javashi, Thanos Stouraitis, Keivan Navi. Efficient RNS Implementation of Elliptic Curve Point Multiplication Over ${\rm GF}(p)$
1549 -- 1553Thinh H. Pham, Suhaib A. Fahmy, Ian Vince McLoughlin. Low-Power Correlation for IEEE 802.16 OFDM Synchronization on FPGA
1554 -- 1557Bosco Leung. Design and Analysis of Saturated Ring Oscillators Based on the Random Mid-Point Voltage Concept
1558 -- 1562Masood Qazi, Mehul Tikekar, Lara Dolecek, Devavrat Shah, Anantha P. Chandrakasan. Technique for Efficient Evaluation of SRAM Timing Failure
1562 -- 1567HoonSeok Kim, Chanyoun Won, Paul D. Franzon. Crosstalk-Canceling Multimode Interconnect Using Transmitter Encoding
1568 -- 1572Milad Mehri, Mohammad Hossein Mazaheri Kouhani, Nasser Masoumi, Reza Sarvari. New Approach to VLSI Buffer Modeling, Considering Overshooting Effect

Volume 21, Issue 7

1181 -- 1188Yalcin Yilmaz, Pinaki Mazumder. Nonvolatile Nanopipelining Logic Using Multiferroic Single-Domain Nanomagnets
1189 -- 1200Jeongha Park, Saeroonter Oh, Soyoung Kim, H.-S. Philip Wong, S. Simon Wong. Impact of III-V and Ge Devices on Circuit Performance
1201 -- 1209Himanshu Thapliyal, Nagarajan Ranganathan, Saurabh Kotiyal. Design of Testable Reversible Sequential Circuits
1210 -- 1219Zijian He, Tao Lv, Huawei Li, Xiaowei Li 0001. Test Path Selection for Capturing Delay Failures Under Statistical Timing Model
1220 -- 1233Ying Zhang, Huawei Li, Xiaowei Li 0001. Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors
1234 -- 1245Minyoung Song, Sunghoon Ahn, Inhwa Jung, Yongtae Kim, Chulwoo Kim. Piecewise Linear Modulation Technique for Spread Spectrum Clock Generation
1246 -- 1259Ting-Chi Tong, Yun-Nan Chang. Efficient Vector Graphics Rasterization Accelerator Using Optimized Scan-Line Buffer
1260 -- 1270Ching-Yi Chen, Sheng-Hung Wang, Cheng-Wen Wu. Write Current Self-Configuration Scheme for MRAM Yield Improvement
1271 -- 1284Wanyong Tian, Yingchao Zhao, Liang Shi, Qing'an Li, Jianhua Li, Chun Jason Xue, Minming Li, Enhong Chen. Task Allocation on Nonvolatile-Memory-Based Hybrid Main Memory
1285 -- 1298Oguzhan Atak, Abdullah Atalar. BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture
1299 -- 1307Vadim Smolyakov, P. Glenn Gulak, Timothy Gallagher, Curtis Ling. Fault-Tolerant Embedded-Memory Strategy for Baseband Signal Processing Systems
1308 -- 1321Hamid Shojaei, Azadeh Davoodi, Twan Basten. Collaborative Multiobjective Global Routing
1322 -- 1332Jienan Chen, JianHao Hu. Energy-Efficient Digital Signal Processing via Voltage-Overscaling-Based Residue Number System
1333 -- 1337Katherine Shu-Min Li, Yi-Yu Liao. IEEE 1500 Compatible Multilevel Maximal Concurrent Interconnect Test
1337 -- 1341Seong-In Hwang, Hanho Lee. Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design
1342 -- 1345Luke Pierce, Spyros Tragoudas. Enhanced Secure Architecture for Joint Action Test Group Systems
1346 -- 1350Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede. Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications
1350 -- 1354Yangyang Pan, Guiqiang Dong, Tong Zhang 0002. Error Rate-Based Wear-Leveling for nand Flash Memory at Highly Scaled Technology Nodes
1354 -- 1359Irith Pomeranz. Reduced Power Transition Fault Test Sets for Circuits With Independent Scan Chain Modes
1359 -- 1363Irith Pomeranz. Transition Fault Simulation Considering Broadside Tests as Partially-Functional Broadside Tests
1364 -- 1368Naveed Imran, Jooheung Lee, Ronald F. DeMara. Fault Demotion Using Reconfigurable Slack (FaDReS)
1368 -- 1373Jung-Hyun Park, Dong-Hoon Jung, Kyungho Ryu, Seong-Ook Jung. ADDLL for Clock-Deskew Buffer in High-Performance SoCs

Volume 21, Issue 6

989 -- 999Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh. Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms
1000 -- 1012Lucas Francisco Wanner, Charwak Apte, Rahul Balani, Puneet Gupta, Mani B. Srivastava. Hardware Variability-Aware Duty Cycling for Embedded Sensors
1013 -- 1026Young-Geun Choi, Sungjoo Yoo, Sunggu Lee, Jung Ho Ahn, Kangmin Lee. MAEPER: Matching Access and Error Patterns With Error-Free Resource for Low Vcc L1 Cache
1027 -- 1040Isaak Yang, Sung Hoon Jung, Kwang-Hyun Cho. Self-Repairing Digital System With Unified Recovery Process Inspired by Endocrine Cellular Communication
1041 -- 1052Kyu-Nam Shim, Jiang Hu, José Silva-Martínez. Dual-Level Adaptive Supply Voltage System for Variation Resilience
1053 -- 1066Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, Zuocheng Xing. Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router
1067 -- 1079Marcel Gort, Jason Helge Anderson. Combined Architecture/Algorithm Approach to Fast FPGA Routing
1080 -- 1093JungHee Lee, Chrysostomos Nicopoulos, Hyung Gyu Lee, Shreepad Panth, Sung Kyu Lim, Jongman Kim. IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures
1094 -- 1102Jingtong Hu, Chun Jason Xue, Qingfeng Zhuge, Wei-Che Tseng, Edwin Hsing-Mean Sha. Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory
1103 -- 1115Eddie Hung, Steven J. E. Wilton. Scalable Signal Selection for Post-Silicon Debug
1116 -- 1128Ender Yilmaz, Sule Ozev, Kenneth M. Butler. Per-Device Adaptive Test for Analog/RF Circuits Using Entropy-Based Process Monitoring
1129 -- 1142Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor. Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects
1143 -- 1153Meng-chou Chang, Wei-Hsiang Chang. Asynchronous Fine-Grain Power-Gated Logic
1154 -- 1164Jun-Ren Su, Te-Wen Liao, Chung-Chih Hung. All-Digital Fast-Locking Pulsewidth-Control Circuit With Programmable Duty Cycle
1165 -- 1169Sumit Jagdish Darak, A. Prasad Vinod, Edmund M.-K. Lai. Efficient Implementation of Reconfigurable Warped Digital Filters With Variable Low-Pass, High-Pass, Bandpass, and Bandstop Responses
1170 -- 1174Christina C.-H. Liao, Allen W.-T. Chen, Louis Y.-Z. Lin, Charles H.-P. Wen. Fast Scan-Chain Ordering for 3-D-IC Designs Under Through-Silicon-Via (TSV) Constraints
1175 -- 1179Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. DDmin-Aware Dual Supply Voltage Technique

Volume 21, Issue 5

793 -- 806Supriya Karmakar, John A. Chandy, Faquir C. Jain. Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs
807 -- 820Haitham Eissa, Rami Fathy Salem, Ahmed Arafa, Sherif Hany, Abdelrahman ElMously, Mohamed Dessouky, David Nairn, Mohab H. Anis. Parametric DFM Solution for Analog Circuits: Electrical-Driven Hotspot Detection, Analysis, and Correction Flow
821 -- 833Song Jin, Yinhe Han, Huawei Li, Xiaowei Li 0001. Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction
834 -- 847Mojtaba Mahdavi, Mahdi Shabany. Novel MIMO Detection Algorithm for High-Order Constellations in the Complex Domain
848 -- 861Mahdi Shabany, Ameer Youssef, P. Glenn Gulak. High-Throughput 0.13-µm CMOS Lattice Reduction Core Supporting 880 Mb/s Detection
862 -- 874Dae-Hyun Kim, Krit Athikulwongse, Sung Kyu Lim. Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout
875 -- 886Shen-Fu Hsiao, Hou-Jen Ko, Yu-Ling Tseng, Wen-Liang Huang, Shin-Hung Lin, Chia-Sheng Wen. Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping
887 -- 900Behnam Ghavami, Mohsen Raji, Hossein Pedram, Massoud Pedram. Statistical Functional Yield Estimation and Enhancement of CNFET-Based VLSI Circuits
901 -- 909Sujoy Sinha Roy, Chester Rebeiro, Debdeep Mukhopadhyay. Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed
910 -- 920Suhaib A. Fahmy, A. R. Mohan. Architecture for Real-Time Nonparametric Probability Density Function Estimation
921 -- 933Jinwook Oh, Seungjin Lee, Hoi-Jun Yoo. 1.2-mW Online Learning Mixed-Mode Intelligent Inference Engine for Low-Power Real-Time Object Recognition Processor
934 -- 943Ali Peiravi, Mohammad Asyaei. Current-Comparison-Based Domino: New Low-Leakage High-Speed Domino Circuit for Wide Fan-In Gates
944 -- 957Zhigang Hao, Guoyong Shi, Sheldon X.-D. Tan, Esteban Tlelo-Cuautle. Symbolic Moment Computation for Statistical Analysis of Large Interconnect Networks
958 -- 970Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel. Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation
971 -- 974Hiroaki Inoue, Takashi Takenaka, Masato Motomura. C-Based Complex Event Processing on Reconfigurable Hardware
974 -- 978Wei Zhang, Hao Wang, Boyang Pan. Reduced-Complexity LCC Reed-Solomon Decoder Based on Unified Syndrome Computation
979 -- 983Asaf Kaizerman, Sagi Fisher, Alexander Fish. Subthreshold Dual Mode Logic
983 -- 987Renatas Jakushokas, Eby G. Friedman. Power Network Optimization Based on Link Breaking Methodology

Volume 21, Issue 4

605 -- 613Kanad Basu, Prabhat Mishra. RATS: Restoration-Aware Trace Signal Selection for Post-Silicon Validation
614 -- 623Feng Liang, Luwen Zhang, ShaoChong Lei, Guohe Zhang, Kaile Gao, Bin Liang. Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes
624 -- 635Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, Soon-Jyh Chang. Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops
636 -- 647Gwo-Long Li, Tzu-Yu Chen, Meng-Wei Shen, Meng-Hsun Wen, Tian-Sheuan Chang. 135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder
648 -- 658Tasreen Charania, Ajoy Opal, Manoj Sachdev. Analysis and Design of On-Chip Decoupling Capacitors
659 -- 669Yupeng Chen, Bertil Schmidt, Douglas L. Maskell. Reconfigurable Accelerator for the Word-Matching Stage of BLASTN
670 -- 679Koushik Chakraborty, Sanghamitra Roy. Architecturally Homogeneous Power-Performance Heterogeneous Multicore Systems
680 -- 691Selçuk Köse, Simon Tam, Sally Pinzon, Bruce McDermott, Eby G. Friedman. Active Filter-Based Hybrid On-Chip DC-DC Converter for Point-of-Load Voltage Regulation
692 -- 705Katherine Shu-Min Li. CusNoC: Fast Full-Chip Custom NoC Generation
706 -- 719Liang Shi, Jianhua Li, Chun Jason Xue, Xuehai Zhou. Cooperating Virtual Memory and Write Buffer Management for Flash-Based Storage Systems
720 -- 731Kai-Jiun Yang, Shang-Ho Tsai, Gene C. H. Chuang. MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems
732 -- 746Hesam Amir Aslanzadeh, Erik John Pankratz, Chinmaya Mishra, Edgar Sánchez-Sinencio. Current-Reused 2.4-GHz Direct-Modulation Transmitter With On-Chip Automatic Tuning
747 -- 760Yen-Liang Chen, Cheng-Zhou Zhan, Ting-Jyun Jheng, An-Yeu Wu. Reconfigurable Adaptive Singular Value Decomposition Engine Design for High-Throughput MIMO-OFDM Systems
761 -- 770David B. Thomas, Wayne Luk. The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures
771 -- 775Yangyang Pan, Yiran Li, Hongbin Sun, Wei Xu, Nanning Zheng, Tong Zhang 0002. Exploring the Use of Emerging Nonvolatile Memory Technologies in Future FPGAs
776 -- 780Irith Pomeranz. Broadside and Skewed-Load Tests Under Primary Input Constraints
781 -- 785Yasuhiro Ogasahara, Masanori Hashimoto, Toshiki Kanamoto, Takao Onoye. Supply Noise Suppression by Triple-Well Structure
786 -- 790Giorgos Theodorou, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos. Software-Based Self Test Methodology for On-Line Testing of L1 Caches in Multithreaded Multicore Architectures
791 -- 0Keshab K. Parhi. Comments on "Low-energy CSMT carry generators and binary adders"

Volume 21, Issue 3

393 -- 412Yehea I. Ismail. Editorial Appointments for the 2013-2014 Term
413 -- 423Shi-Hao Chen, Youn-Long Lin, Mango Chia-Tso Chao. Power-Up Sequence Control for MTCMOS Designs
424 -- 433S. Man Ho Ho, Yanqing Ai, Thomas Chun-Pong Chau, Steve C. L. Yuen, Oliver Chiu-sing Choy, Philip Heng Wai Leong, Kong-Pang Pun. Architecture and Design Flow for a Highly Efficient Structured ASIC
434 -- 442Santosh Ghosh, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury. Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform
443 -- 453Jhih-Wei You, Shi-Yu Huang, Yu-Hsiang Lin, Meng-Hsiu Tsai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu. In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis
454 -- 464Sehun Kook, Hyun Woo Choi, Abhijit Chatterjee. Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements
465 -- 474Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting Cheng, Cheng-Wen Wu. Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers
475 -- 485Irith Pomeranz. Computing Two-Pattern Test Cubes for Transition Path Delay Faults
486 -- 497Erin G. Fong, Nathaniel J. Guilar, Travis Kleeburg, Hai Pham, Diego R. Yankelevich, Rajeevan Amirtharajah. Integrated Energy-Harvesting Photodiodes With Diffractive Storage Capacitance
498 -- 511Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro. Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool
512 -- 522Josep Rius. IR-Drop in On-Chip Power Distribution Networks of ICs With Nonuniform Power Consumption
523 -- 532Cha-Ru Li, Wai-Kei Mak, Ting-Chi Wang. Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement
533 -- 545Hailong Jiao, Volkan Kursun. Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits
546 -- 553Kwan Wai Li, Ka Nang Leung, Lincoln Lai Kan Leung. Sub-mW $LC$ Dual-Input Injection-Locked Oscillator for Autonomous WBSNs
554 -- 565Pierce Chuang, David Li, Manoj Sachdev. Constant Delay Logic Style
566 -- 570Sebastian Höppner, Holger Eisenreich, Stephan Henker, Dennis Walter, Georg Ellguth, René Schüffny. A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology
571 -- 574Emad Ebrahimi, Sasan Naseh. A Colpitts CMOS Quadrature VCO Using Direct Connection of Substrates for Coupling
575 -- 579Sewook Hwang, Kyeong-Min Kim, Jungmoon Kim, Seon Wook Kim, Chulwoo Kim. A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor
580 -- 584Abhishek A. Sinkar, Taejoon Park, Nam Sung Kim. Clamping Virtual Supply Voltage of Power-Gated Circuits for Active Leakage Reduction and Gate-Oxide Reliability
584 -- 588Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin. 10-bit 30-MS/s SAR ADC Using a Switchback Switching Method
589 -- 592Te-Wen Liao, Jun-Ren Su, Chung-Chih Hung. Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD
593 -- 596Xiwen Zhang, Hoi Lee. Gain-Enhanced Monolithic Charge Pump With Simultaneous Dynamic Gate and Substrate Control
597 -- 601Jinn-Shyan Wang, Keng-Jui Chang, Chingwei Yeh, Shih-Chieh Chang. Embedding Repeaters in Silicon IPs for Cross-IP Interconnections

Volume 21, Issue 2

193 -- 205Davide Rossi, Claudio Mucci, Fabio Campi, Simone Spolzino, Luca Vanzolini, Henning Sahlbach, Sean Whitty, Rolf Ernst, Wolfram Putzke-Röming, Roberto Guerrieri. Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor
206 -- 216Jae-Sung Yoon, Jeong Hyun Kim, Hyo-Eun Kim, Won Young Lee, Seok-Hoon Kim, Kyusik Chung, Jun-Seok Park, Lee-Sup Kim. A Unified Graphics and Vision Processor With a 0.89 µW/fps Pose Estimation Engine for Augmented Reality
217 -- 228Pramod Kumar Meher, Sang Yoon Park. CORDIC Designs for Fixed Angle of Rotation
229 -- 238Yoshi Shih-Chieh Huang, Kaven Chun-Kai Chou, Chung-Ta King. Application-Driven End-to-End Traffic Predictions for Low Power NoC Design
239 -- 249Yuanqing Cheng, Lei Zhang 0008, Yinhe Han, Xiaowei Li 0001. Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs
250 -- 258I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu. A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS
259 -- 269Ransford Hyman Jr., Nagarajan Ranganathan, Thomas Bingel, Deanne Tran Vo. A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering
270 -- 280You-Gang Chen, Hen-Wai Tsao, Chorng-Sii Hwang. A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction
281 -- 291Jaeyong Chung, Joonsung Park, Jacob A. Abraham. A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories
292 -- 305Yaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang 0012, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Weichen Liu. System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip
306 -- 319Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel. A Study of Tapered 3-D TSVs for Power and Thermal Integrity
320 -- 328Joon-Sung Yang, Nur A. Touba. Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug
329 -- 341Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu. AC-Plus Scan Methodology for Small Delay Testing and Characterization
342 -- 353Marshnil Vipin Dave, Mahavir Jain, Maryam Shojaei Baghini, Dinesh Kumar Sharma. A Variation Tolerant Current-Mode Signaling Scheme for On-Chip Interconnects
354 -- 366Xiang Hu, Peng Du, James F. Buckwalter, Chung-Kuan Cheng. Modeling and Analysis of Power Distribution Networks in 3-D ICs
367 -- 379Kai-Chiang Wu, Diana Marculescu. A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits
380 -- 384Siddhesh S. Mhambrey, Satendra Kumar Maurya, Lawrence T. Clark. Low Complexity Out-of-Order Issue Logic Using Static Circuits
385 -- 389Jiafeng Xie, Jianjun He, Pramod Kumar Meher. Low Latency Systolic Montgomery Multiplier for Finite Field $GF(2^{m})$ Based on Pentanomials

Volume 21, Issue 12

2165 -- 2178Dawood Alnajiar, Hiroaki Konoura, Younghun Ko, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye. Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture
2179 -- 2192Ying Wang, Xuegong Zhou, Lingli Wang, Jian Yan, Wayne Luk, Chenglian Peng, Jiarong Tong. SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model
2193 -- 2205David B. Thomas, Wayne Luk. Multiplierless Algorithm for Multivariate Gaussian Random Number Generation in FPGAs
2206 -- 2213Hyo-Jin Kim, Tai-Ji An, Sung-Meen Myung, Seung-Hoon Lee. Time-Interleaved and Circuit-Shared Dual-Channel 10 b 200 MS/s 0.18 $\mu{\rm m}$ CMOS Analog-to-Digital Convertor
2214 -- 2225Sangwoo Han, Byung-Su Kim, Juho Kim. Variation-Aware Aging Analysis in Digital ICs
2226 -- 2239Hu Xu, Vasilis F. Pavlidis, Xifan Tang, Wayne Burleson, Giovanni De Micheli. Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise
2240 -- 2249Pei-Ying Chao, Chao-Wen Tzeng, Shi-Yu Huang, Chia-Chieh Weng, Shan Chien Fang. Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping
2250 -- 2261Wei Li, Dian Zhou, Minghua Li, Binh P. Nguyen, Xuan Zeng. Near-Field Communication Transceiver System Modeling and Analysis Using SystemC/SystemC-AMS With the Consideration of Noise Issues
2262 -- 2273Liang Liu, Johan Löfgren, Peter Nilsson, Viktor Öwall. VLSI Implementation of a Soft-Output Signal Detector for Multimode Adaptive Multiple-Input Multiple-Output Systems
2274 -- 2285Yuxiang Zheng, Jin Liu, Robert Payne, Mark Morgan, Hoi Lee. A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13-$\mu{\rm m}$ CMOS
2286 -- 2294Martin Omaña, Daniele Rossi, Daniele Giaffreda, Roberto Specchia, Cecilia Metra, Marcin Marzencki, Bozena Kaminska. Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection
2295 -- 2306Dusko Karaklajic, Jörn-Marc Schmidt, Ingrid Verbauwhede. Hardware Designer's Guide to Fault Attacks
2307 -- 2320Justin S. Wong, Peter Y. K. Cheung. Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability
2321 -- 2325Irith Pomeranz. Functional Broadside Templates for Low-Power Test Generation
2325 -- 2330Jun Han, Shuai Wang, Wei Huang, Zhiyi Yu, Xiaoyang Zeng. Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform
2330 -- 2333Hossein Mahdizadeh, Massoud Masoumi. Novel Architecture for Efficient FPGA Implementation of Elliptic Curve Cryptographic Processor Over ${\rm GF}(2^{163})$
2334 -- 2338Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro. Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation
2338 -- 2343Katherine Shu-Min Li. Oscillation and Transition Tests for Synchronous Sequential Circuits
2343 -- 2348Xin Zhao, Ahmet T. Erdogan, Tughrul Arslan. High-Efficiency Customized Coarse-Grained Dynamically Reconfigurable Architecture for JPEG2000
2348 -- 2352Ruo-Ting Ding, Shi-Yu Huang, Chao-Wen Tzeng. Cell-Based Process Resilient Multiphase Clock Generation
2353 -- 2357Natan Krihely, Sam Ben-Yaakov, Alexander Fish. Efficiency Optimization of a Step-Down Switched Capacitor Converter for Subthreshold

Volume 21, Issue 11

1965 -- 1974Thomas Plos, Michael Hutter, Martin Feldhofer, M. Stiglic, F. Cavaliere. Security-Enabled Near-Field Communication Tag With Flexible Architecture Supporting Asymmetric Cryptography
1975 -- 1988Ajay N. Bhoj, Niraj K. Jha. Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology
1989 -- 1998Saleh Abdel-Hafeez, Ann Gordon-Ross, B. Parhami. Scalable Digital CMOS Comparator Using a Parallel Prefix Tree
1999 -- 2009Shiann-Rong Kuang, Jiun-Ping Wang, Kai-Cheng Chang, Huan-Wei Hsu. Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems
2010 -- 2023Fang Cai, Xinmiao Zhang. Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes
2024 -- 2033Nicolas Laflamme-Mayer, Walder Andre, Olivier Valorge, Yves Blaquière, M. Sawan. Configurable Input-Output Power Pad for Wafer-Scale Microelectronic Systems
2034 -- 2044Vikram Chaturvedi, T. Anand, Bharadwaj Amrutur. An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording
2045 -- 2054Bing Shi, Yufu Zhang, Ankur Srivastava. Dynamic Thermal Management Under Soft Thermal Constraints
2055 -- 2068Chia-Chun Lin, A. Chakrabarti, N. K. Jha. Optimized Quantum Gate Library for Various Physical Machine Descriptions
2069 -- 2079B. Mohammad, D. Homouz, H. Elgabra. Robust Hybrid Memristor-CMOS Memory: Modeling and Design
2080 -- 2093Minyoung Song, Young-Ho Kwak, Sunghoon Ahn, Hojin Park, Chulwoo Kim. 10-315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation
2094 -- 2105Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha. 3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits
2106 -- 2117A. Kapoor, J. P. de Gyvez. Architectural Analysis for Wirelessly Powered Computing Platforms
2118 -- 2131Chih-Hao Chao, Kun-Chih Chen, An-Yeu Wu. Routing-Based Traffic Migration and Buffer Allocation Schemes for 3-D Network-on-Chip Systems With Thermal Limit
2132 -- 2140Hing-Kit Kwan, D. C. W. Ng, V. W. K. So. Design and Analysis of Dual-Mode Digital-Control Step-Up Switched-Capacitor Power Converter With Pulse-Skipping and Numerically Controlled Oscillator-Based Frequency Modulation
2141 -- 2154Dominic DiTomaso, Randy Morris, Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri. Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips
2155 -- 2159Jang-Woo Lee, Hong-Jung Kim, Chun-Seok Jeong, Jae-Jin Lee, Changsik Yoo. Skew Compensation Technique for Source-Synchronous Parallel DRAM Interface
2160 -- 2164Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee. Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation

Volume 21, Issue 10

1769 -- 1782Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori. Enhancing the Efficiency of Energy-Constrained DVFS Designs
1783 -- 1796Eun Ju Hwang, Wook Kim, Young-Hwan Kim. Timing Yield Slack for Timing Yield-Constrained Optimization and Its Application to Statistical Leakage Minimization
1797 -- 1810Ching-Te Chiu, Wen-Chih Huang, Chih-Hsing Lin, Wei-Chih Lai, Ying-Fang Tsao. Embedded Transition Inversion Coding With Low Switching Activity for Serial Links
1811 -- 1822Rajeev Narayanan, Ibtissem Seghaier, Mohamed H. Zaki, Sofiène Tahar. Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process Variation
1823 -- 1836Yiyuan Xie, Mahdi Nikdast, Jiang Xu, Xiaowen Wu, Wei Zhang 0012, Yaoyao Ye, Xuan Wang, Zhehui Wang, Weichen Liu. Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip
1837 -- 1848Austin C.-C. Chang, Ryan H.-M. Huang, Charles H.-P. Wen. CASSER: A Closed-Form Analysis Framework for Statistical Soft Error Rate
1849 -- 1862Mohammed Shoaib, Niraj K. Jha, Naveen Verma. Algorithm-Driven Architectural Design Space Exploration of Domain-Specific Medical-Sensor Processors
1863 -- 1877Hyunhee Kim, Jung Ho Ahn, Jihong Kim. Exploiting Replicated Cache Blocks to Reduce L2 Cache Leakage in CMPs
1878 -- 1891Mohammad Samie, Gabriel Dragffy, Andy M. Tyrrell, Tony Pipe, Paul Bremner. Novel Bio-Inspired Approach for Fault-Tolerant VLSI Systems
1892 -- 1902Feng Shi, Xuebin Wu, Zhiyuan Yan. New Crosstalk Avoidance Codes Based on a Novel Pattern Classification
1903 -- 1914Siddharth Garg, Diana Marculescu. Mitigating the Impact of Process Variation on the Performance of 3-D Integrated Circuits
1915 -- 1927Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede. Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems
1928 -- 1935Shanshan Dai, Xiaofei Cao, Ting Yi, Allyn E. Hubbard, Zhiliang Hong. 1-V Low-Power Programmable Rail-to-Rail Operational Amplifier With Improved Transconductance Feedback Technique
1936 -- 1940Thian Fatt Tay, Chip-Hong Chang, Jeremy Yung Shern Low. Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n}, 2^{n}+1\}}$
1941 -- 1945Seyed E. Esmaeili, Asim J. Al-Kahlili. Integrated Power and Clock Distribution Network
1945 -- 1949Leonel Sousa, Samuel Antao, Ricardo Chaves. On the Design of RNS Reverse Converters for the Four-Moduli Set ${\bf\{2^{\mmb n}+1, 2^{\mmb n}-1, 2^{\mmb n}, 2^{{\mmb n}+1}+1\}}$
1950 -- 1954Kisoo Kim, HoKyu Lee, Chulwoo Kim. 366-kS/s 1.09-nJ 0.0013-${\rm mm}^{2}$ Frequency-to-Digital Converter Based CMOS Temperature Sensor Utilizing Multiphase Clock
1955 -- 1959Pekka Miettinen, Mikko Honkala, Janne Roos, Martti Valtonen. Sparsification of Dense Capacitive Coupling of Interconnect Models
1960 -- 1964Yang Sun, Joseph R. Cavallaro. VLSI Architecture for Layered Decoding of QC-LDPC Codes With High Circulant Weight

Volume 21, Issue 1

1 -- 13Dong Hyuk Woo, Nak Hee Seong, Hsien-Hsin S. Lee. Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV
14 -- 22Liang Li, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo. A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks
23 -- 32Mario Garrido, Jesús Grajal, M. A. Sanchez, Oscar Gustafsson. k Feedforward FFT Architectures
33 -- 42Jui-Hung Hsieh, Tian-Sheuan Chang. Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time Mobile Video Applications
43 -- 54Hsiao-Yun Chen, Jyun-Nan Lin, Hsiang-Sheng Hu, Shyh-Jye Jou. STBC-OFDM Downlink Baseband Receiver for Mobile WMAN
55 -- 66Davide De Caro. Glitch-Free NAND-Based Digitally Controlled Delay-Lines
67 -- 77Po-Hsiang Lan, Tsung-Ju Yang, Po-Chiun Huang. A High-Efficiency, Wide Workload Range, Digital Off-Time Modulation (DOTM) DC-DC Converter With Asynchronous Power Saving Technique
78 -- 91Aritra Hazra, Sahil Goyal, Pallab Dasgupta, Ajit Pal. Formal Verification of Architectural Power Intent
92 -- 101Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry. Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits
102 -- 112Jianwei Dai, Lei Wang 0003. An Energy-Efficient L2 Cache Architecture Using Way Tag Information Under Write-Through Policy
113 -- 123Abbas Eslami Kiasari, Zhonghai Lu, Axel Jantsch. An Analytical Latency Model for Networks-on-Chip
124 -- 132Irith Pomeranz. Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure
133 -- 141Marius Monton, Jakob Engblom, Mark Burton. Checkpointing for Virtual Platforms and SystemC-TLM
142 -- 147Tsang-Chi Kan, Shih Hsien Yang, Ting-Feng Chang, Shanq-Jang Ruan. Design of a Practical Nanometer-Scale Redundant Via-Aware Standard Cell Library for Improved Redundant Via1 Insertion Rate
147 -- 151Bo Marr, Brian P. Degnan, Paul E. Hasler, David V. Anderson. Scaling Energy Per Operation via an Asynchronous Pipeline
151 -- 156Anh-Tuan Do, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo. A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing
156 -- 159Pedro Reviriego, Juan Antonio Maestro, Mark F. Flanagan. Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes
159 -- 163Yunus Emre, Chaitali Chakrabarti. Techniques for Compensating Memory Errors in JPEG2000
164 -- 168Kan Takeuchi, Masaki Shimada, Takao Sato, Yusaku Katsuki, Hiroumi Yoshikawa, Hiroaki Matsushita. Spatial Distribution Measurement of Dynamic Voltage Drop Caused by Pulse and Periodic Injection of Spot Noise
168 -- 173Jiafeng Xie, Pramod Kumar Meher, Jianjun He. m) Based on All-One Polynomials
173 -- 177Phi-Hung Pham, Junyoung Song, Jongsun Park, Chulwoo Kim. Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip
178 -- 182Phi-Hung Pham, Phuong Mau, Jungmoon Kim, Chulwoo Kim. An On-Chip Network Fabric Supporting Coarse-Grained Processor Array
182 -- 187J. A. Galan, Manuel Pedro, Trinidad Sanchez-Rodriguez, F. Munoz, Ramón González Carvajal, Antonio J. López-Martín. A Very Linear Low-Pass Filter with Automatic Frequency Tuning
187 -- 191Taesang Cho, Hanho Lee. 5 FFT Processor for High Rate WPAN Applications