| 1573 | -- | 1582 | Guoqing Deng, Chunhong Chen. Binary Multiplication Using Hybrid MOS and Multi-Gate Single-Electron Transistors |
| 1583 | -- | 1595 | Dongsoo Lee, Kaushik Roy. Area Efficient ROM-Embedded SRAM Cache |
| 1596 | -- | 1607 | Chengwu Tao, Ayman A. Fayed. PWM Control Architecture With Constant Cycle Frequency Hopping and Phase Chopping for Spur-Free Operation in Buck Regulators |
| 1608 | -- | 1618 | Jiann-Jong Chen, Ming-Xiang Lu, Tse-Hsu Wu, Yuh-Shyan Hwang. Sub-1-V Fast-Response Hysteresis-Controlled CMOS Buck Converter Using Adaptive Ramp Techniques |
| 1619 | -- | 1631 | Kyu-Nam Shim, Jiang Hu. Boostable Repeater Design for Variation Resilience in VLSI Interconnects |
| 1632 | -- | 1643 | Yoonmyung Lee, Daeyeon Kim, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, David Blaauw, Dennis Sylvester. Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs) |
| 1644 | -- | 1654 | Won-Ho Park, Chih-Kong Ken Yang. Effects of Using Advanced Cooling Systems on the Overall Power Consumption of Processors |
| 1655 | -- | 1668 | Yanheng Zhang, Chris Chu. RegularRoute: An Efficient Detailed Router Applying Regular Routing Patterns |
| 1669 | -- | 1682 | Chun-Yi Lee, Niraj K. Jha. Variable-Pipeline-Stage Router |
| 1683 | -- | 1692 | Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown. Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection |
| 1693 | -- | 1704 | Kalarikkal Absel, Lijo Manuel, R. K. Kavitha. Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic |
| 1705 | -- | 1714 | Irith Pomeranz. On Test Compaction of Broadside and Skewed-Load Test Cubes |
| 1715 | -- | 1726 | Jaeyong Chung, Jacob A. Abraham. Concurrent Path Selection Algorithm in Statistical Timing Analysis |
| 1727 | -- | 1737 | Chi-Ying Lee, Chih-Cheng Hsieh, Jenn-Chyou Bor. 2.4-GHz 10-Mb/s BFSK Embedded Transmitter With a Stacked-LC DCO for Wireless Testing Systems |
| 1738 | -- | 1742 | Guoqing Deng, Chunhong Chen. A SET/MOS Hybrid Multiplier Using Frequency Synthesis |
| 1742 | -- | 1747 | Chia-Min Chen, Tung-Wei Tsai, Chung-Chih Hung. Fast Transient Low-Dropout Voltage Regulator With Hybrid Dynamic Biasing Technique for SoC Application |
| 1747 | -- | 1751 | Shaowei Zhen, Xiaohui Zhu, Ping Luo, Yajuan He, Bo Zhang. Digital Error Corrector for Phase Lead-Compensated Buck Converter in DVS Applications |
| 1751 | -- | 1756 | Yanheng Zhang, Chris Chu. Fast and Effective Placement Refinement for Routability |
| 1756 | -- | 1761 | Jun Lin, Zhiyuan Yan. Efficient Shuffled Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes |
| 1762 | -- | 1766 | Samah Mohamed Saeed, Ozgur Sinanoglu, Sobeeh Almukhaizim. Predictive Techniques for Projecting Test Data Volume Compression |