| 1181 | -- | 1188 | Yalcin Yilmaz, Pinaki Mazumder. Nonvolatile Nanopipelining Logic Using Multiferroic Single-Domain Nanomagnets |
| 1189 | -- | 1200 | Jeongha Park, Saeroonter Oh, Soyoung Kim, H.-S. Philip Wong, S. Simon Wong. Impact of III-V and Ge Devices on Circuit Performance |
| 1201 | -- | 1209 | Himanshu Thapliyal, Nagarajan Ranganathan, Saurabh Kotiyal. Design of Testable Reversible Sequential Circuits |
| 1210 | -- | 1219 | Zijian He, Tao Lv, Huawei Li, Xiaowei Li 0001. Test Path Selection for Capturing Delay Failures Under Statistical Timing Model |
| 1220 | -- | 1233 | Ying Zhang, Huawei Li, Xiaowei Li 0001. Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors |
| 1234 | -- | 1245 | Minyoung Song, Sunghoon Ahn, Inhwa Jung, Yongtae Kim, Chulwoo Kim. Piecewise Linear Modulation Technique for Spread Spectrum Clock Generation |
| 1246 | -- | 1259 | Ting-Chi Tong, Yun-Nan Chang. Efficient Vector Graphics Rasterization Accelerator Using Optimized Scan-Line Buffer |
| 1260 | -- | 1270 | Ching-Yi Chen, Sheng-Hung Wang, Cheng-Wen Wu. Write Current Self-Configuration Scheme for MRAM Yield Improvement |
| 1271 | -- | 1284 | Wanyong Tian, Yingchao Zhao, Liang Shi, Qing'an Li, Jianhua Li, Chun Jason Xue, Minming Li, Enhong Chen. Task Allocation on Nonvolatile-Memory-Based Hybrid Main Memory |
| 1285 | -- | 1298 | Oguzhan Atak, Abdullah Atalar. BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture |
| 1299 | -- | 1307 | Vadim Smolyakov, P. Glenn Gulak, Timothy Gallagher, Curtis Ling. Fault-Tolerant Embedded-Memory Strategy for Baseband Signal Processing Systems |
| 1308 | -- | 1321 | Hamid Shojaei, Azadeh Davoodi, Twan Basten. Collaborative Multiobjective Global Routing |
| 1322 | -- | 1332 | Jienan Chen, JianHao Hu. Energy-Efficient Digital Signal Processing via Voltage-Overscaling-Based Residue Number System |
| 1333 | -- | 1337 | Katherine Shu-Min Li, Yi-Yu Liao. IEEE 1500 Compatible Multilevel Maximal Concurrent Interconnect Test |
| 1337 | -- | 1341 | Seong-In Hwang, Hanho Lee. Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design |
| 1342 | -- | 1345 | Luke Pierce, Spyros Tragoudas. Enhanced Secure Architecture for Joint Action Test Group Systems |
| 1346 | -- | 1350 | Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede. Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications |
| 1350 | -- | 1354 | Yangyang Pan, Guiqiang Dong, Tong Zhang 0002. Error Rate-Based Wear-Leveling for nand Flash Memory at Highly Scaled Technology Nodes |
| 1354 | -- | 1359 | Irith Pomeranz. Reduced Power Transition Fault Test Sets for Circuits With Independent Scan Chain Modes |
| 1359 | -- | 1363 | Irith Pomeranz. Transition Fault Simulation Considering Broadside Tests as Partially-Functional Broadside Tests |
| 1364 | -- | 1368 | Naveed Imran, Jooheung Lee, Ronald F. DeMara. Fault Demotion Using Reconfigurable Slack (FaDReS) |
| 1368 | -- | 1373 | Jung-Hyun Park, Dong-Hoon Jung, Kyungho Ryu, Seong-Ook Jung. ADDLL for Clock-Deskew Buffer in High-Performance SoCs |