| 1 | -- | 13 | Dong Hyuk Woo, Nak Hee Seong, Hsien-Hsin S. Lee. Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV |
| 14 | -- | 22 | Liang Li, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo. A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks |
| 23 | -- | 32 | Mario Garrido, Jesús Grajal, M. A. Sanchez, Oscar Gustafsson. k Feedforward FFT Architectures |
| 33 | -- | 42 | Jui-Hung Hsieh, Tian-Sheuan Chang. Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time Mobile Video Applications |
| 43 | -- | 54 | Hsiao-Yun Chen, Jyun-Nan Lin, Hsiang-Sheng Hu, Shyh-Jye Jou. STBC-OFDM Downlink Baseband Receiver for Mobile WMAN |
| 55 | -- | 66 | Davide De Caro. Glitch-Free NAND-Based Digitally Controlled Delay-Lines |
| 67 | -- | 77 | Po-Hsiang Lan, Tsung-Ju Yang, Po-Chiun Huang. A High-Efficiency, Wide Workload Range, Digital Off-Time Modulation (DOTM) DC-DC Converter With Asynchronous Power Saving Technique |
| 78 | -- | 91 | Aritra Hazra, Sahil Goyal, Pallab Dasgupta, Ajit Pal. Formal Verification of Architectural Power Intent |
| 92 | -- | 101 | Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry. Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits |
| 102 | -- | 112 | Jianwei Dai, Lei Wang 0003. An Energy-Efficient L2 Cache Architecture Using Way Tag Information Under Write-Through Policy |
| 113 | -- | 123 | Abbas Eslami Kiasari, Zhonghai Lu, Axel Jantsch. An Analytical Latency Model for Networks-on-Chip |
| 124 | -- | 132 | Irith Pomeranz. Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure |
| 133 | -- | 141 | Marius Monton, Jakob Engblom, Mark Burton. Checkpointing for Virtual Platforms and SystemC-TLM |
| 142 | -- | 147 | Tsang-Chi Kan, Shih Hsien Yang, Ting-Feng Chang, Shanq-Jang Ruan. Design of a Practical Nanometer-Scale Redundant Via-Aware Standard Cell Library for Improved Redundant Via1 Insertion Rate |
| 147 | -- | 151 | Bo Marr, Brian P. Degnan, Paul E. Hasler, David V. Anderson. Scaling Energy Per Operation via an Asynchronous Pipeline |
| 151 | -- | 156 | Anh-Tuan Do, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo. A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing |
| 156 | -- | 159 | Pedro Reviriego, Juan Antonio Maestro, Mark F. Flanagan. Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes |
| 159 | -- | 163 | Yunus Emre, Chaitali Chakrabarti. Techniques for Compensating Memory Errors in JPEG2000 |
| 164 | -- | 168 | Kan Takeuchi, Masaki Shimada, Takao Sato, Yusaku Katsuki, Hiroumi Yoshikawa, Hiroaki Matsushita. Spatial Distribution Measurement of Dynamic Voltage Drop Caused by Pulse and Periodic Injection of Spot Noise |
| 168 | -- | 173 | Jiafeng Xie, Pramod Kumar Meher, Jianjun He. m) Based on All-One Polynomials |
| 173 | -- | 177 | Phi-Hung Pham, Junyoung Song, Jongsun Park, Chulwoo Kim. Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip |
| 178 | -- | 182 | Phi-Hung Pham, Phuong Mau, Jungmoon Kim, Chulwoo Kim. An On-Chip Network Fabric Supporting Coarse-Grained Processor Array |
| 182 | -- | 187 | J. A. Galan, Manuel Pedro, Trinidad Sanchez-Rodriguez, F. Munoz, Ramón González Carvajal, Antonio J. López-Martín. A Very Linear Low-Pass Filter with Automatic Frequency Tuning |
| 187 | -- | 191 | Taesang Cho, Hanho Lee. 5 FFT Processor for High Rate WPAN Applications |