| 989 | -- | 999 | Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh. Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms |
| 1000 | -- | 1012 | Lucas Francisco Wanner, Charwak Apte, Rahul Balani, Puneet Gupta, Mani B. Srivastava. Hardware Variability-Aware Duty Cycling for Embedded Sensors |
| 1013 | -- | 1026 | Young-Geun Choi, Sungjoo Yoo, Sunggu Lee, Jung Ho Ahn, Kangmin Lee. MAEPER: Matching Access and Error Patterns With Error-Free Resource for Low Vcc L1 Cache |
| 1027 | -- | 1040 | Isaak Yang, Sung Hoon Jung, Kwang-Hyun Cho. Self-Repairing Digital System With Unified Recovery Process Inspired by Endocrine Cellular Communication |
| 1041 | -- | 1052 | Kyu-Nam Shim, Jiang Hu, José Silva-MartÃnez. Dual-Level Adaptive Supply Voltage System for Variation Resilience |
| 1053 | -- | 1066 | Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, Zuocheng Xing. Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router |
| 1067 | -- | 1079 | Marcel Gort, Jason Helge Anderson. Combined Architecture/Algorithm Approach to Fast FPGA Routing |
| 1080 | -- | 1093 | JungHee Lee, Chrysostomos Nicopoulos, Hyung Gyu Lee, Shreepad Panth, Sung Kyu Lim, Jongman Kim. IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures |
| 1094 | -- | 1102 | Jingtong Hu, Chun Jason Xue, Qingfeng Zhuge, Wei-Che Tseng, Edwin Hsing-Mean Sha. Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory |
| 1103 | -- | 1115 | Eddie Hung, Steven J. E. Wilton. Scalable Signal Selection for Post-Silicon Debug |
| 1116 | -- | 1128 | Ender Yilmaz, Sule Ozev, Kenneth M. Butler. Per-Device Adaptive Test for Analog/RF Circuits Using Entropy-Based Process Monitoring |
| 1129 | -- | 1142 | Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor. Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects |
| 1143 | -- | 1153 | Meng-chou Chang, Wei-Hsiang Chang. Asynchronous Fine-Grain Power-Gated Logic |
| 1154 | -- | 1164 | Jun-Ren Su, Te-Wen Liao, Chung-Chih Hung. All-Digital Fast-Locking Pulsewidth-Control Circuit With Programmable Duty Cycle |
| 1165 | -- | 1169 | Sumit Jagdish Darak, A. Prasad Vinod, Edmund M.-K. Lai. Efficient Implementation of Reconfigurable Warped Digital Filters With Variable Low-Pass, High-Pass, Bandpass, and Bandstop Responses |
| 1170 | -- | 1174 | Christina C.-H. Liao, Allen W.-T. Chen, Louis Y.-Z. Lin, Charles H.-P. Wen. Fast Scan-Chain Ordering for 3-D-IC Designs Under Through-Silicon-Via (TSV) Constraints |
| 1175 | -- | 1179 | Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. DDmin-Aware Dual Supply Voltage Technique |