| 1133 | -- | 1143 | Xuecheng Wang, Yahao Song, Fengfan Hou, Milin Zhang, Andrew G. Richardson, Timothy H. Lucas, Jan Van der Spiegel. Design of a Real-Time Movement Decomposition-Based Rodent Tracker and Behavioral Analyzer Based on FPGA |
| 1144 | -- | 1157 | Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee. A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks |
| 1158 | -- | 1171 | Tengfei Wang, Chi Zhang, Pei Cao, Dawu Gu. Efficient Implementation of Dilithium Signature Scheme on FPGA SoC Platform |
| 1172 | -- | 1183 | Sina Sayyah Ensan, Swaroop Ghosh, Seyedhamidreza Motaman, Derek Weast. Addressing Resiliency of In-Memory Floating Point Computation |
| 1184 | -- | 1192 | Yu-Hsiang Chiang, Tian-Sheuan Chang, Shyh-Jye Jou. A 14 μJ/Decision Keyword-Spotting Accelerator With In-SRAMComputing and On-Chip Learning for Customization |
| 1193 | -- | 1206 | Zihao Xuan, Yi Kang. High-Efficiency Data Conversion Interface for Reconfigurable Function-in-Memory Computing |
| 1207 | -- | 1218 | Nitin Pundir, Jungmin Park, Farimah Farahmandi, Mark M. Tehranipoor. Power Side-Channel Leakage Assessment Framework at Register-Transfer Level |
| 1219 | -- | 1229 | Arijit Nath, Hemangee K. Kapoor. Pop-Crypt: Identification and Management of Popular Words for Enhancing Lifetime of EnCrypted Nonvolatile Main Memories |
| 1230 | -- | 1243 | Theodros Nigussie, Joshua Schabel, Steve Lipa, Lisa G. McIlrath, Robert Patti, Paul D. Franzon. Design Obfuscation Through 3-D Split Fabrication With Smart Partitioning |
| 1244 | -- | 1255 | Frank T. Werner, Milos Prvulovic, Alenka G. Zajic. Detection of Recycled ICs Using Backscattering Side-Channel Analysis |
| 1256 | -- | 1268 | Yale Wang, Chenghua Wang, Chongyan Gu, Yijun Cui, Máire O'Neill, Weiqiang Liu. A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs |
| 1269 | -- | 1280 | Youngmin Park, Dongsuk Jeon. A 270-mA Self-Calibrating-Clocked Output-Capacitor-Free LDO With 0.15-1.15V Output Range and 0.183-fs FoM |
| 1281 | -- | 1293 | Indranil Bhattacharjee, Gajendranath Chowdary. A 0.3 nW, 0.093%/V Line Sensitivity, Temperature Compensated Bulk-Programmable Voltage Reference for Wireless Sensor Nodes |
| 1294 | -- | 1305 | S. Babak Hamidi, Debasis Dawn. A New Pathway Toward Implementing a Fully Integrated Band-Switchable CMOS Power Amplifier Utilizing Bit Optimized Reconfigurable Network (BORN) |
| 1306 | -- | 1318 | Xiaorui Zhu, Yihan Qian, Zhixiang Peng, Yimin Liang, Shengxi Diao. Analysis and Design of a DC-12-GHz Distribution Power Amplifier for Quantum Key Distribution Application |
| 1319 | -- | 1331 | Hamed Nasiri, Cheng Li 0005, Lihong Zhang. Ultra-Low Power SAR ADC Using Statistical Characteristics of Low-Activity Signals |
| 1332 | -- | 1340 | Smrutilekha Samanta, Santanu Sarkar 0002. A Pairwise Swap Enabled Randomized DEM Addressing Intersegment Mismatch for Current Steering Digital-to-Analog Converters |
| 1341 | -- | 1354 | Aaron C.-W. Liang, Charles H.-P. Wen, Hsuan-Ming Huang. A General and Automatic Cell Layout Generation Framework With Implicit Learning on Design Rules |
| 1355 | -- | 1367 | Sai Pentapati, Sung Kyu Lim. Metal Layer Sharing: A Routing Optimization Technique for Monolithic 3D ICs |
| 1368 | -- | 1372 | Yuxing Chen, Hangxuan Cui, Zhongfeng Wang. An Efficient Reconfigurable Encoder for the IEEE 1901 Standard |