Journal: IEEE Trans. VLSI Syst.

Volume 30, Issue 9

1133 -- 1143Xuecheng Wang, Yahao Song, Fengfan Hou, Milin Zhang, Andrew G. Richardson, Timothy H. Lucas, Jan Van der Spiegel. Design of a Real-Time Movement Decomposition-Based Rodent Tracker and Behavioral Analyzer Based on FPGA
1144 -- 1157Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee. A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks
1158 -- 1171Tengfei Wang, Chi Zhang, Pei Cao, Dawu Gu. Efficient Implementation of Dilithium Signature Scheme on FPGA SoC Platform
1172 -- 1183Sina Sayyah Ensan, Swaroop Ghosh, Seyedhamidreza Motaman, Derek Weast. Addressing Resiliency of In-Memory Floating Point Computation
1184 -- 1192Yu-Hsiang Chiang, Tian-Sheuan Chang, Shyh-Jye Jou. A 14 μJ/Decision Keyword-Spotting Accelerator With In-SRAMComputing and On-Chip Learning for Customization
1193 -- 1206Zihao Xuan, Yi Kang. High-Efficiency Data Conversion Interface for Reconfigurable Function-in-Memory Computing
1207 -- 1218Nitin Pundir, Jungmin Park, Farimah Farahmandi, Mark M. Tehranipoor. Power Side-Channel Leakage Assessment Framework at Register-Transfer Level
1219 -- 1229Arijit Nath, Hemangee K. Kapoor. Pop-Crypt: Identification and Management of Popular Words for Enhancing Lifetime of EnCrypted Nonvolatile Main Memories
1230 -- 1243Theodros Nigussie, Joshua Schabel, Steve Lipa, Lisa G. McIlrath, Robert Patti, Paul D. Franzon. Design Obfuscation Through 3-D Split Fabrication With Smart Partitioning
1244 -- 1255Frank T. Werner, Milos Prvulovic, Alenka G. Zajic. Detection of Recycled ICs Using Backscattering Side-Channel Analysis
1256 -- 1268Yale Wang, Chenghua Wang, Chongyan Gu, Yijun Cui, Máire O'Neill, Weiqiang Liu. A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs
1269 -- 1280Youngmin Park, Dongsuk Jeon. A 270-mA Self-Calibrating-Clocked Output-Capacitor-Free LDO With 0.15-1.15V Output Range and 0.183-fs FoM
1281 -- 1293Indranil Bhattacharjee, Gajendranath Chowdary. A 0.3 nW, 0.093%/V Line Sensitivity, Temperature Compensated Bulk-Programmable Voltage Reference for Wireless Sensor Nodes
1294 -- 1305S. Babak Hamidi, Debasis Dawn. A New Pathway Toward Implementing a Fully Integrated Band-Switchable CMOS Power Amplifier Utilizing Bit Optimized Reconfigurable Network (BORN)
1306 -- 1318Xiaorui Zhu, Yihan Qian, Zhixiang Peng, Yimin Liang, Shengxi Diao. Analysis and Design of a DC-12-GHz Distribution Power Amplifier for Quantum Key Distribution Application
1319 -- 1331Hamed Nasiri, Cheng Li 0005, Lihong Zhang. Ultra-Low Power SAR ADC Using Statistical Characteristics of Low-Activity Signals
1332 -- 1340Smrutilekha Samanta, Santanu Sarkar 0002. A Pairwise Swap Enabled Randomized DEM Addressing Intersegment Mismatch for Current Steering Digital-to-Analog Converters
1341 -- 1354Aaron C.-W. Liang, Charles H.-P. Wen, Hsuan-Ming Huang. A General and Automatic Cell Layout Generation Framework With Implicit Learning on Design Rules
1355 -- 1367Sai Pentapati, Sung Kyu Lim. Metal Layer Sharing: A Routing Optimization Technique for Monolithic 3D ICs
1368 -- 1372Yuxing Chen, Hangxuan Cui, Zhongfeng Wang. An Efficient Reconfigurable Encoder for the IEEE 1901 Standard

Volume 30, Issue 8

993 -- 1006Yang Su, Bai-Long Yang, Chen Yang 0005, Zepeng Yang, Yi-Wei Liu. A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication
1007 -- 1019Dongdong Xu, Xiang Wang 0006, Yuanchao Hao, Zhun Zhang, Qiang Hao, Zhiyu Zhou. A More Accurate and Robust Binary Ring-LWE Decryption Scheme and Its Hardware Implementation for IoT Devices
1020 -- 1033Rahul Sharma, Rahul Shrestha, Satinder K. Sharma. Low-Latency and Reconfigurable VLSI-Architectures for Computing Eigenvalues and Eigenvectors Using CORDIC-Based Parallel Jacobi Method
1034 -- 1046Jinming Lu, Jian Huang, Zhongfeng Wang. THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration
1047 -- 1058Yichuan Bai, Mingzhe Jiang, Qingyu Zhu, Xiaoliang Chen, Yuan Du, Li Du, Zhongfeng Wang. An Efficient High-Throughput Structured-Light Depth Engine
1059 -- 1072Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Daeyeal Lee, Bill Lin 0001. Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis
1073 -- 1083Naveen Kumar Macha, Bhavana Tejaswini Repalle, Md Arif Iqbal, Mostafizur Rahman. Crosstalk-Computing-Based Gate-Level Reconfigurable Circuits
1084 -- 1097Baver Ozceylan, Boudewijn R. Haverkort, Maurits de Graaf, Marco E. T. Gerards. Minimizing the Maximum Processor Temperature by Temperature-Aware Scheduling of Real-Time Tasks
1098 -- 1106Fereshteh Kalantari, Hossein Hosseini-Nejad, Amir M. Sodagar. Hardware-Efficient, On-the-Fly, On-Implant Spike Sorter Dedicated to Brain-Implantable Microsystems
1107 -- 1118Wei Xiong, Gang Dong, Yang Wang, Zhangming Zhu, Yintang Yang. 3-D Compact Marchand Balun Design Based on Through-Silicon via Technology for Monolithic and 3-D Integration
1119 -- 1132Yu-Hsuan Lee, Yu-Hsing Chiu, Szu-Hsuan Lai, Wen-Yu Chiou, Yue-Fang Kuo. A Design of 12.8-Gpixels/s Hardware-Efficient Lossless Embedded Compression Engine for Video Coding Applications

Volume 30, Issue 7

849 -- 859Yuyang Li, Yawen Wu, Xincheng Zhang, Jingtong Hu, Inhee Lee. Energy-Aware Adaptive Multi-Exit Neural Network Inference Implementation for a Millimeter-Scale Sensing System
860 -- 868Paria Darbani, Nezam Rohbani, Hakem Beitollahi, Pejman Lotfi-Kamran. RASHT: A Partially Reconfigurable Architecture for Efficient Implementation of CNNs
869 -- 880Khaled Alhaj Ali, Amer Baghdadi, Elsa Dupraz, Mathieu Léonardon, Mostafa Rizk, Jean-Philippe Diguet. MOL-Based In-Memory Computing of Binary Neural Networks
881 -- 892Kashif Inayat, Jaeyong Chung. Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration
893 -- 904Daney Alex, Vinay Chakravarthi Gogineni, Subrahmanyam Mula, Stefan Werner 0001. Novel VLSI Architecture for Fractional-Order Correntropy Adaptive Filtering Algorithm
905 -- 914Yao-Hung Tsai, Shen-Iuan Liu. 2 12-bit 20-MS/s SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS
915 -- 925Dong Hyun Yoon, Dong-Kyu Jung, Kiho Seong, Jae-Soub Han, Keun-Yong Chung, Ju Eon Kim, Tony Tae-Hyoung Kim, Kwang-Hyun Baek. rms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier
926 -- 937Hammond Pearce, Virinchi Roy Surabhi, Prashanth Krishnamurthy, Joshua Trujillo, Ramesh Karri, Farshad Khorrami. Detecting Hardware Trojans in PCBs Using Side Channel Loopbacks
938 -- 951Kerem Arikan, Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Salvatore Pontarelli, Giuseppe Bianchi 0001, Oguz Ergin, Marco Ottavi. Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches
952 -- 965Subodha Charles, Vincent Bindschaedler, Prabhat Mishra 0001. Digital Watermarking for Detecting Malicious Intellectual Property Cores in NoC Architectures
966 -- 974Feng Qiu, Haoshen Zhu, Wenquan Che, Quan Xue. A Simplified Vector-Sum Phase Shifter Topology With Low Noise Figure and High Voltage Gain
975 -- 988Shuo-Wen Chang, Yu-Teng Nien, Yu-Pang Hu, Kai-Chiang Wu, Chi-Chun Wang, Fu-Sheng Huang, Yi-Lun Tang, Yung-Chen Chen, Ming-Chien Chen, Mango C.-T. Chao. Test Methodology for Defect-Based Bridge Faults
989 -- 992Fengjuan Wang, Kai Zhang, Xiangkun Yin, Ningmei Yu, Yuan Yang 0006. A Miniaturized Wideband Interdigital Bandpass Filter With High Out-Band Suppression Based on TSV Technology for W-Band Application

Volume 30, Issue 6

681 -- 693Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine, Warren J. Gross. High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND
694 -- 705Yiming Yu, Dong Chen, Xiaoning Zhang, Chenxi Zhao, Huihua Liu, Yunqiu Wu, Wen-Yan Yin, Kai Kang. A Ku-Band Eight-Element Phased-Array Transmitter With Built-in Self-Test Capability in 180-nm CMOS Technology
706 -- 719Yao Li, Bo Zhou 0004, Fuyuan Zhao, Yujie Liu, Yeran Jin. A 1.15-mW Low-Power Low-Complexity Reconfigurable FM-UWB Transmitter
720 -- 731Naina Singhal, S. M. Rezaul Hasan. A 25-30-GHz RMS Error-Minimized 360° Continuous Analog Phase Shifter Using Closed-Loop Self-Tuning I/Q Generator
732 -- 743Xiaolong Liu, Howard C. Luong. Analysis and Design of Magnetically Tuned W -Band Oscillators
744 -- 754Ningcheng GaoDing, Jean-François Bousquet. A 4th-Order 4-Bit Continuous-Time ΔΣ ADC Based on Active-Passive Integrators With a Resistance Feedback DAC
755 -- 768Souvik Kundu 0001, Priyanka B. Ganganaik, Jeffry Louis, Hemanth Chalamalasetty, BVVSN Prabhakar Rao. Memristors Enabled Computing Correlation Parameter In-Memory System: A Potential Alternative to Von Neumann Architecture
769 -- 780Jian Chen, Wenfeng Zhao, Yuqi Wang, Yuhao Shu, Weixiong Jiang, Yajun Ha. A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations
781 -- 793Hayoung Lee, Younwoo Yoo, Seung-Ho Shin, Sungho Kang. ECMO: ECC Architecture Reusing Content-Addressable Memories for Obtaining High Reliability in DRAM
794 -- 802Ausmita Sarker, Mehran Mozaffari Kermani, Reza Azarderakhsh. Efficient Error Detection Architectures for Postquantum Signature Falcon's Sampler and KEM SABER
803 -- 815Ziying Ni, Dur-e-Shahwar Kundi, Máire O'Neill, Weiqiang Liu. A High-Performance SIKE Hardware Accelerator
816 -- 825Kuo-Wei Chang, Hsu-Tung Shih, Tian-Sheuan Chang, Shang-Hong Tsai, Chih-Chyau Yang, Chien-Ming Wu, Chun-Ming Huang. A Real-Time 1280 × 720 Object Detection Chip With 585 MB/s Memory Traffic
826 -- 839Sina Ghaffari, David W. Capson, Kin Fun Li. A Fully Pipelined FPGA Architecture for Multiscale BRISK Descriptors With a Novel Hardware-Aware Sampling Pattern
840 -- 843Youngwoo Ji, Jae-Yoon Sim. A 20.5-nW Resistor-Less Bandgap Voltage Reference With Self-Biased Compensation for Process Variations
844 -- 848Mohamadreza Zolfagharinejad, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram. Posit Process Element for Using in Energy-Efficient DNN Accelerators

Volume 30, Issue 5

553 -- 565Dayane Reis, Haoran Geng, Michael T. Niemier, Xiaobo Sharon Hu. IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption
566 -- 578Yue Zhao, Zhiting Lin, Xiulong Wu, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Zhongzhen Tong, Junning Chen. Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing
579 -- 588Dai Li, Akhil Reddy Pakala, Kaiyuan Yang 0001. MeNTT: A Compact and Efficient Processing-in-Memory Number Theoretic Transform (NTT) Accelerator
589 -- 602Hayssam El-Razouk. m) Polynomial Basis Multiplication
603 -- 614Madhan Thirumoorthi, Moslem Heidarpur, Mitra Mirhassani, Mohammed A. S. Khalid. An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic
615 -- 624Sandeep Goyal, Ganpat Anant Parulekar, Shalabh Gupta. A True Full-Duplex IO (TFD-IO) With Background SI Cancellation for High-Density Interfaces
625 -- 633Yulang Feng, Hao Deng, Qingjun Fan, Yuxuan Tang, Phaneendra Bikkina, Esko Mikkola, Jinghong Chen. A 5-GS/s 6-Bit 15.07-mW Flash ADC With Partially Active Second-Stage Comparison and 2× Time-Domain Interpolation
634 -- 643Yan-Ting Chen, Pen-Jui Peng, Hung-Wen Lin. A 12-14.5-GHz 10.2-mW -249-dB FoM Fractional-N Subsampling PLL With a High-Linearity Phase Interpolator in 40-nm CMOS
644 -- 655Qihui Zhang, Ning Ning 0002, Zhong Zhang 0002, Jing Li 0022, Kejun Wu, Qi Yu 0002. A 12-Bit Two-Step Single-Slope ADC With a Constant Input-Common-Mode Level Resistor Ramp Generator
656 -- 660Yuhao Chen, Hongge Li. Stochastic Computing Using Amplitude and Frequency Encoding
661 -- 665Hesheng Lin, Dimitrios Velenis, Philip Nolmans, Xiao Sun, Francky Catthoor, Rudy Lauwereins, Geert Van der Plas, Eric Beyne. 84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor
666 -- 670Shatadal Chatterjee, Sounak Roy. A Self-Calibration Method of a Pipeline ADC Based on Dynamic Capacitance Allotment
671 -- 675Biswabandhu Jana, Pallab Kumar Nath. A Single-Chip Solution for Diagnosing Peripheral Arterial Disease
676 -- 680Yuting Chen, Yuxuan Nie, Hailong Jiao. An Ultralow-Power 65-nm Standard Cell Library for Near/Subthreshold Digital Circuits

Volume 30, Issue 4

353 -- 364Leilei Jin, Wenjie Fu, Ming Ling, Longxing Shi. A Fast Cross-Layer Dynamic Power Estimation Method by Tracking Cycle-Accurate Activity Factors With Spark Streaming
365 -- 378Sandeep Krishna Thirumala, Arnab Raha, Sumeet Kumar Gupta, Vijay Raghunathan. Exploring the Design of Energy-Efficient Intermittently Powered Systems Using Reconfigurable Ferroelectric Transistors
379 -- 391Yewei Zhang, Kejie Huang, Rui Xiao, Bo Wang, Yanfeng Xu, Jicong Fan, Haibin Shen. An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping
392 -- 405Mengyun Liu, Krishnendu Chakrabarty. Online Fault Detection in ReRAM-Based Computing Systems for Inferencing
406 -- 417Laxmeesha Somappa, Maryam Shojaei Baghini. Continuous-Time Hybrid ΔΣ Modulators for Sub-μW Power Multichannel Biomedical Applications
418 -- 431Dawen Xu 0002, Zhuangyu Feng, Cheng Liu 0008, Li Li, Ying Wang 0001, Huawei Li, Xiaowei Li 0001. Taming Process Variations in CNFET for Efficient Last-Level Cache Design
432 -- 439Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, JaeHyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni 0004, Peter Debacker, Asen Asenov, Aida Todri-Sanial. Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization
440 -- 448Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, JaeHyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni 0004, Peter Debacker, Asen Asenov, Aida Todri-Sanial. Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization
449 -- 462Atul Prasad Deb Nath, Kshitij Raj, Swarup Bhunia, Sandip Ray. SoCCom: Automated Synthesis of System-on-Chip Architectures
463 -- 473Yi Tan, Yohsuke Shiiki, Hiroki Ishikuro. Optimization of Gate Voltage in Capacitive DC-DC Converters for Thermoelectric Energy Harvesting
474 -- 487Rui Yao, Yinhua Zhao, Yongchuan Yu, Yihe Zhao, Xueyan Zhong. Fast Search and Efficient Placement Algorithm for Reconfigurable Tasks on Modern Heterogeneous FPGAs
488 -- 501Mesala M. Sravani, Ananiah Durai Sundararajan. On Efficiency Enhancement of SHA-3 for FPGA-Based Multimodal Biometric Authentication
502 -- 514Weixiong Jiang, Heng Yu 0001, Hongtu Zhang, Yuhao Shu, Rui Li, Jian Chen, Yajun Ha. FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA
515 -- 525Hassan Salmani. Gradual-N-Justification (GNJ) to Reduce False-Positive Hardware Trojan Detection in Gate-Level Netlist
526 -- 538Eslam Elmitwalli, Kai Ni 0004, Selçuk Köse. Machine Learning Attack Resistant Area-Efficient Reconfigurable Ising-PUF
539 -- 543Abdullah Ibn Abbas, Glenn E. R. Cowan. A Receiver Front-End for VCSEL-Based Optical Links With 49 UI Turn-On Time
544 -- 548Fei Lyu 0002, Yan Xia, Yuheng Chen, Yanxu Wang, Yuanyong Luo, Yu Wang. High-Throughput Low-Latency Pipelined Divider for Single-Precision Floating-Point Numbers
549 -- 552Erfan Bank-Tavakoli, Amir Beygi, Xuebin Yao. RPkNN: An OpenCL-Based FPGA Implementation of the Dimensionality-Reduced kNN Algorithm Using Random Projection

Volume 30, Issue 3

253 -- 266Nakisa Shams, Frederic Nabki. Analysis and Comparison of Low-Power 6-GHz N-Path-Filter-Based Harmonic Selection RF Receiver Front-End Architectures
267 -- 276Jinhai Xiao, Ning Liang, BingWen Chen, Maliang Liu. rms Jitter and Fast Frequency Hopping
277 -- 290Mahesh Kumar Adimulam, M. B. Srinivas. A 12-bit, 1.1-GS/s, Low-Power Flash ADC
291 -- 302Zhen Gao, Han Zhang, Yi Yao, Jiajun Xiao, Shulin Zeng, Guangjun Ge, Yu Wang 0002, Anees Ullah, Pedro Reviriego. Soft Error Tolerant Convolutional Neural Networks on FPGAs With Ensemble Learning
303 -- 314Kasem Khalil, Omar Eldash, Ashok Kumar 0001, Magdy A. Bayoumi. Designing Novel AAD Pooling in Hardware for a Convolutional Neural Network Accelerator
315 -- 324Hamidreza Esmaeili Taheri, Mitra Mirhassani. A Pre-Activation, Golden IC Free, Hardware Trojan Detection Approach
325 -- 338Shuo Yang, Tamzidul Hoque, Prabuddha Chakraborty, Swarup Bhunia. Golden-Free Hardware Trojan Detection Using Self-Referencing
339 -- 352Divya Praneetha Ravipati, Rajesh Kedia, Victor M. van Santen, Jörg Henkel, Preeti Ranjan Panda, Hussam Amrouch. FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies

Volume 30, Issue 2

113 -- 122Lianxi Liu, Yaling Ji, Xufeng Liao, Zhenghe Qin, Hongzhi Liang. A 0.8-V, 2.55-GHz, 2.62-mW Charge-Pump PLL With High Spectrum Purity
123 -- 133Liang Fang, Xianshan Wen, Tao Fu, Guanhua Wang, Sandeep Miryala, Tiehui Ted Liu, Ping Gui. S in 65-nm CMOS
134 -- 142Zhong Zhang 0002, Qi Yu 0002, Qihui Zhang, Jing Li 0022, Kejun Wu, Ning Ning 0002. A Code-Recombination Algorithm-Based ADC With Feature Extraction for WBSN Applications
143 -- 152Jahyun Koo 0001, Jae-Yoon Sim. Low-Noise Distributed RC Oscillator
153 -- 165Shinya Kajiyama, Yutaka Igarashi, Toru Yazaki, Yusaku Katsube, Takuma Nishimoto, Tatsuo Nakagawa, Yohei Nakamura, Yoshihiro Hayashi, Takuya Kaneko, Hiroki Ishikuro, Taizo Yamawaki. T/R Switch Composed of Three HV-MOSFETs With 12.1-μW Consumption That Enables Per-Channel Self-Loopback AC Tests and -18.1-dB Switching Noise Suppression for 3-D Ultrasound Imaging With 3072-Ch Transceiver
166 -- 176Rohit B. Chaurasiya, Rahul Shrestha. Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network
177 -- 186Pietro Nannipieri, Stefano Di Matteo, Luca Baldanzi, Luca Crocetti, Luca Zulberti, Sergio Saponara, Luca Fanucci. VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative
187 -- 200Trevor Kroeger, Wei Cheng, Sylvain Guilley, Jean-Luc Danger, Naghmeh Karimi. Assessment and Mitigation of Power Side-Channel-Based Cross-PUF Attacks on Arbiter-PUFs and Their Derivatives
201 -- 212Dionysios Filippas, Nikolaos Margomenos, Nikolaos Mitianoudis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos. Low-Cost Online Convolution Checksum Checker
213 -- 226Wei Mao, Kai Li, Quan Cheng, Liuyao Dai, Boyu Li, Xinang Xie, He Li 0008, Longyang Lin, Hao Yu 0001. A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing
227 -- 237Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Andrew Boutros, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Wayne Luk. Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs
238 -- 242Zunsong Yang, Yong Chen 0005, Jia Yuan, Pui-In Mak, Rui Paulo Martins. A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM
243 -- 247Botao Xiong, Yukun Li, Sicun Li, Sheng Fan, Yuchun Chang. Half-Precision Logarithmic Arithmetic Unit Based on the Fused Logarithmic and Antilogarithmic Converter
248 -- 252Yosef Lempel, Rinat Breuer, Joseph Shor. A 700-μm², Ring-Oscillator-Based Thermal Sensor in 16-nm FinFET

Volume 30, Issue 12

1813 -- 1826Zhen Li, Su Zheng, Jide Zhang, Yao Lu, Jingbo Gao, Jun Tao 0001, Lingli Wang. Adaptable Approximate Multiplier Design Based on Input Distribution and Polarity
1827 -- 1839Zhufei Chu, Chuanhe Shang, Tingting Zhang, Yinshui Xia, Lunyao Wang, Weiqiang Liu. Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits
1840 -- 1852Hsi-Hung Lu, Chung-An Shen, Mohammed E. Fouda, Ahmed M. Eltawil. Configurable Independent Component Analysis Preprocessing Accelerator
1853 -- 1866Zhe-Yu Wang, Pei-Yun Tsai. Design and Implementation of a 6.5-Gb/s Multiradix Simplified Viterbi-Sphere Decoder for Trellis-Coded Generalized Spatial Modulation With Spatial Multiplexing
1867 -- 1877Zhongyang Liu, Haineng Zhang, Jianwei Jiang, Yanjie Jia, Yuqiao Xie, Shichang Zou, Zhengxuan Zhang. A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch Design
1878 -- 1890Wei Mao 0002, Liuyao Dai, Kai Li, Quan Cheng, Yuhang Wang, Laimin Du, Shaobo Luo, Mingqiang Huang, Hao Yu 0001. An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks
1891 -- 1901Md. Najrul Islam, Rahul Shrestha, Shubhajit Roy Chowdhury. An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks
1902 -- 1915Chen Yang 0005, Yishuo Meng, Kaibo Huo, Jiawei Xi, Kuizhi Mei. A Sparse CNN Accelerator for Eliminating Redundant Computations in Intra- and Inter-Convolutional/Pooling Layers
1916 -- 1927Muhammad Rizwan Khan, Rameesha Qaiser, Wala Saadeh. A 380-μW Electrochemical Impedance Measurement System for Protein Sensing
1928 -- 1932Hanrui Zhang, Xiaofei Wang, Nannan Li, Zihao Jiao, Liang Chen, Di Mu, Jie Zhang, Hong Zhang 0009. A 2.5-MHz BW, 75-dB SNDR Noise-Shaping SAR ADC With a 1st-Order Hybrid EF-CIFF Structure Assisted by Unity-Gain Buffer

Volume 30, Issue 11

1573 -- 1586Chao Fang, Aojun Zhou, Zhongfeng Wang. An Algorithm-Hardware Co-Optimized Framework for Accelerating N: M Sparse Transformers
1587 -- 1600Shengzhao Li, Qin Wang 0009, Jianfei Jiang 0001, Weiguang Sheng, Naifeng Jing, Zhigang Mao. An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs
1601 -- 1614Abhishek Ramdas Nair, Pallab Kumar Nath, Shantanu Chakrabartty, Chetan Singh Thakur. Multiplierless MP-Kernel Machine for Energy-Efficient Edge Devices
1615 -- 1630Mustafa Fayez Ali, Sourjya Roy, Utkarsh Saxena, Tanvi Sharma, Anand Raghunathan, Kaushik Roy 0001. Compute-in-Memory Technologies and Architectures for Deep Learning Workloads
1631 -- 1641Yisong Kuang, Xiaoxin Cui, Zilin Wang, Chenglong Zou, Yi Zhong, Kefei Liu 0002, Zhenhui Dai, Dunshan Yu, Yuan Wang 0001, Ru Huang. ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator
1642 -- 1653Wenzhe Guo, Mohammed E. Fouda, Ahmed M. Eltawil, Khaled Nabil Salama. Efficient Neuromorphic Hardware Through Spiking Temporal Online Local Learning
1654 -- 1667Krithika Dhananjay, Vasilis F. Pavlidis, Ayse K. Coskun, Emre Salman. High Bandwidth Thermal Covert Channel in 3-D-Integrated Multicore Processors
1668 -- 1676Sankatali Venkateswarlu, Subrat Mishra, Herman Oprins, Bjorn Vermeersch, Moritz Brunion, Jun-Han Han, Mircea R. Stan, Pieter Weckx, Francky Catthoor. Thermal Performance Analysis of Mempool RISC-V Multicore SoC
1677 -- 1690Ying Zhang 0040, Yi Ding, Zebo Peng, Huawei Li, Masahiro Fujita, Jianhui Jiang. BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature
1691 -- 1704Xiao Hu, Minghao Li, Jing Tian 0004, Zhongfeng Wang. Efficient Homomorphic Convolution Designs on FPGA for Secure Inference
1705 -- 1715Kleber Stangherlin, Manoj Sachdev. Design and Implementation of a Secure RISC-V Microprocessor
1716 -- 1727Seyed Hamidreza Moghadas, Michael Pehl, Georg Sigl. ROPAD: Enhancing the Digital Ring Oscillator Probing Attempt Detector for Protecting Irregular Data Buses
1728 -- 1738Hyunho Park, Hanwool Jeong. Self-Shut-Off Pulsed Latches for Minimizing Sequencing Overhead
1739 -- 1747Fabian Khateb, Tomasz Kulej, Meysam Akbari, Kea-Tiong Tang. A 0.5-V Multiple-Input Bulk-Driven OTA in 0.18-μm CMOS
1748 -- 1756Hesheng Lin, Geert Van der Plas, Xiao Sun, Dimitrios Velenis, Francky Catthoor, Rudy Lauwereins, Eric Beyne. Efficient Backside Power Delivery for High-Performance Computing Systems
1757 -- 1769Ji-Yung Lin, Pieter Weckx, Subrat Mishra, Alessio Spessot, Francky Catthoor. Multitimescale Mitigation for Performance Variability Improvement in Time-Critical Systems
1770 -- 1782Xiaoyang Ma, Hongtao Zhong, Nuo Xiu, Yiming Chen, Guodong Yin, Vijaykrishnan Narayanan, Yongpan Liu, Kai Ni 0004, Huazhong Yang, Xueqing Li. CapCAM: A Multilevel Capacitive Content Addressable Memory for High-Accuracy and High-Scalability Search and Compute Applications
1783 -- 1793Jai-Ming Lin, Liang-Chi Zane, Min-Chia Tsai, Yung-Chen Chen, Che-Li Lin, Chen-Fa Tsai. PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability
1794 -- 1802Mubeen Zafar, Muhammad Naeem Awais, Muhammad Naeem Shehzad, Abbas Javed. CEVGMM: Computationally Efficient Versatile Generic Memristor Model
1803 -- 1807Irith Pomeranz. Functional Test Sequences as a Source for Partially Functional Launch-on-Shift Tests
1808 -- 1812Wen Xun Lian, Harikrishnan Ramiah, Gabriel Chong, Kishore Kumar Pakkirisami Churchill, Nai Shyan Lai, Yong Chen 0005, Pui-In Mak, Rui Paulo Martins. A -20-dBm Sensitivity RF Energy-Harvesting Rectifier Front End Using a Transformer IMN

Volume 30, Issue 10

1373 -- 1380Andrei A. Antonov, Maksim S. Karpovich, Vladislav Yu. Vasilyev. Power-On Reset Circuit in 180-nm CMOS With Brownout Detection, Stable Switching Points, Long Reset Pulse Duration, and Resilience to Switching Noise
1381 -- 1390Young Ha Hwang, Yoonho Song, Jun-Eun Park, Deog Kyoon Jeong. A Fully Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques
1391 -- 1400Xingyuan Tong, Dong Liu, Ronghua Wang. A 12-Bit Current-Steering DAC With Unary- Splitting -Binary Segmented Architecture and Improved Decoding Circuit Topology
1401 -- 1411Rozhin Yasaei, Sina Faezi, Mohammad Abdullah Al Faruque. Golden Reference-Free Hardware Trojan Localization Using Graph Convolutional Network
1412 -- 1424Mahmudul Hasan 0012, Jonathan Cruz, Prabuddha Chakraborty, Swarup Bhunia, Tamzidul Hoque. Trojan Resilient Computing in COTS Processors Under Zero Trust
1425 -- 1437Qinyu Chen, Chang Gao, Yuxiang Fu. Cerebron: A Reconfigurable Architecture for Spatiotemporal Sparse Spiking Neural Networks
1438 -- 1447Arash Fouman Ajirlou, Farid Kenarangi, Eli Shapira, Inna Partin-Vaisband. NoD: A Neural Network-Over-Decoder for Edge Intelligence
1448 -- 1460Chun Tao, Deboleena Roy, Indranil Chakraborty, Kaushik Roy 0001. On Noise Stability and Robustness of Adversarially Trained Networks on NVM Crossbars
1461 -- 1472Inho Lee, Yangki Lee, Hongjun Um, Seongmin Hong, Yongjun Park 0001. Dynamic Rate Neural Acceleration Using Multiprocessing Mode Support
1473 -- 1483Prasanna Kumar Saragada, Bishnu Prasad Das. In-Memory Computation With Improved Linearity Using Adaptive Sparsity-Based Compact Thermometric Code
1484 -- 1496Eleni Maragkoudaki, William B. Toms, Vasilis F. Pavlidis. Energy-Efficient Encoding for High-Speed Serial Interfaces
1497 -- 1506Giuliano Sisto, Odysseas Zografos, Bilal Chehab, Naveen Kakarla, Yang Xiang, Dragomir Milojevic, Pieter Weckx, Geert Hellings, Julien Ryckaert. Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era
1507 -- 1518Zhen Wang, Guofa Zhang, Peng Liu 0045, Jing Ye, Jianhui Jiang. Accurate Reliability Boundary Evaluation of Approximate Arithmetic Circuit
1519 -- 1532Jin-Tai Yan. Fixed-Order Placement of Pipelined Architecture in Rapid Single-Flux-Quantum Circuits
1533 -- 1537Alexander Choo Chia Chun, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Yong Chen 0005, Saad Mekhilef, Pui-In Mak, Rui Paulo Martins. 2 FoM for RF-Based Hybrid Energy Harvesting
1538 -- 1542Jacob Atkinson, Anthony Bailey, Armin Tajalli. DS Methodology
1543 -- 1547Irith Pomeranz. Preponing Fault Detections for Test Compaction Under Transparent Scan
1548 -- 1552Abolfazl Zokaei, Dmitri V. Truhachev, Kamal El-Sankary. Memory Optimized Hardware Implementation of Open FEC Encoder
1553 -- 1557Suwen Song, Hangxuan Cui, Zhongfeng Wang. A Universal Efficient Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders
1558 -- 1562Dengquan Li, Lei Zhao, Longsheng Wang, Yi Shen 0007, Zhangming Zhu. A Fast Convergence Second-Order Compensation for Timing Skew in Time-Interleaved ADCs
1563 -- 1567Zhenshan Xie, Yok Jye Tang, Xinmiao Zhang. Low-Latency Nested Decoding for Short Generalized Integrated Interleaved BCH Codes
1568 -- 1572Irith Pomeranz. Test Sequences for Faults in the Scan Logic

Volume 30, Issue 1

1 -- 4Massimo Alioto. Editorial Opening of the 2022 TVLSI Editorial Year - Connecting Trends From Society to VLSI Systems
5 -- 14Makoto Nagata, Takuji Miki, Noriyuki Miura. Physical Attack Protection Techniques for IC Chip Level Hardware Security
15 -- 28Tuotian Liao, Lihong Zhang. High-Dimensional Many-Objective Bayesian Optimization for LDE-Aware Analog IC Sizing
29 -- 39Yue-Ming Wu, Yu-Hsien Kao, Ta-Shun Chu. A 68-GHz Loss Compensated Distributed Amplifier Using Frequency Interleaved Technique in 65-nm CMOS Technology
40 -- 50Ragh Kuttappa, Longfei Wang, Selçuk Köse, Baris Taskin. Multiphase Digital Low-Dropout Regulators
51 -- 59Ghassem Jaberipur, Farzad Ghazanfari. Impact of Radix-10 Redundant Digit Set [-6, 9] on Basic Decimal Arithmetic Operations
60 -- 67Nicholas A. Lanzillo, Albert Chu, Prasad Bhosale, Dan J. Dechene. Power Delivery Design, Signal Routing, and Performance of On-Chip Cobalt Interconnects in Advanced Technology Nodes
68 -- 80Priyesh Shukla, Ankith Muralidhar, Nick Iliev, Theja Tulabandhula, Sawyer B. Fuller, Amit Ranjan Trivedi. Ultralow-Power Localization of Insect-Scale Drones: Interplay of Probabilistic Filtering and Compute-in-Memory
81 -- 94Ning-Chi Huang, Chao-Wei Cheng, Kai-Chiang Wu. Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs
95 -- 107Weidong Zhang, Zhenxing Dong, Yan Zhu. EddySuperblock: Improving NAND Flash Efficiency and Lifetime by Endurance-Driven Dynamic Superblock Management
108 -- 111Sumit Walia, Bachu Varun Tej, Arpita Kabra, Joydeep Kumar Devnath, Joycee Mekie. Fast and Low-Power Quantized Fixed Posit High-Accuracy DNN Implementation
112 -- 0Moslem Heidarpur, Mitra Mirhassani. Corrections to "An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FPGA Implementation"