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Dawen Xu 0002, Zhuangyu Feng, Cheng Liu 0008, Li Li, Ying Wang 0001, Huawei Li, Xiaowei Li 0001. Taming Process Variations in CNFET for Efficient Last-Level Cache Design. IEEE Trans. VLSI Syst., 30(4):418-431, 2022. [doi]
Abstract is missing.