| 5 | -- | 0 | Earl E. Swartzlander Jr.. Editorial |
| 9 | -- | 24 | S. C. Knowles, John G. McWhirter, Roger F. Woods, John V. McCanny. Bit-Level systolic architectures for high performance IIR filtering |
| 25 | -- | 34 | Takao Nishitani, Ichiro Tamitani, Hidenobu Harasaki, Yukio Endo, Toshiyuki Kanou, Koichi Kikuchi. Parallel video signal processor configuration based on overlap-save technique and its LSI processor element: VISP |
| 35 | -- | 43 | Nader Gharachorloo, Satish Gupta, Erdem Hokenek, Peruvemba Balasubramanian, William Bogholtz, Christian Mathieu, Christos Zoulas. A million transistor systolic array graphics engine |
| 45 | -- | 56 | K. Wojtek Przytula, J. Greg Nash. Parallel implementation of synthetic aperture radar algorithms |
| 57 | -- | 67 | Mitsuo Ishii, Hiroyuki Sato, Morio Ikesaka, Kouichi Murakami, Hiroaki Ishihata. Cellular array processor CAP and applications |
| 69 | -- | 84 | R. M. Lea. ASP modules: cost-effective building-blocks for real-time DSP systems |