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    Journal: VLSI Signal Processing

    Volume 1, Issue 4

    257 -- 264Giuseppe Alia, Enrico Martinelli. A VLSI structure for::::X::::(mod::::m::::) operation
    265 -- 278Jef L. van Meerbergen, Jos Huisken, Paul E. R. Lippens, O. McArdle, R. Segers, Gert Goossens, J. Vanhoof, Dirk Lanneer, Francky Catthoor, Hugo De Man. An integrated automatic design system for complex DSP algorithms
    279 -- 285R. Schreiber. Bidiagonalization and symmetric tridiagonalization by systolic arrays
    287 -- 306Francky Catthoor, Dirk Lanneer, Hugo De Man. Efficient microcoded processor design for fixed rate DFT and FFT
    307 -- 320Oscar H. Ibarra, Tao Jiang, Jik H. Chang, Michael A. Palis. Systolic algorithms for some scheduling and graph problems
    321 -- 334Mary Jane Irwin, Robert Michael Owens. A case for digit serial VLSI signal processors
    335 -- 343V. K. Prasanna Kumar, Yu-Chen Tsai. Mapping dynamic programming onto a linear systolic array
    345 -- 365Teresa H. Y. Meng, Robert W. Brodersen, David G. Messerschmitt. A clock-free chip set for high-sampling rate adaptive filters
    367 -- 385D. Bout, Paul D. Franzon, J. Paulos, T. Miller, W. Snyder, T. Nagle, Wentai Liu. Scalable VLSI implementations for neural networks

    Volume 1, Issue 3

    6 -- 0J.-N. Hwang, S. Y. Kung. Parallel algorithms/architectures for neural networks
    167 -- 0Earl E. Swartzlander Jr.. Editorial
    181 -- 188Franklin T. Luk, Eric K. Torng, Cynthia J. Anfinson. A novel fault tolerance technique for recursive least squares minimization
    189 -- 207Graham A. Jullien, P. D. Bird, J. T. Carr, M. Taheri, William C. Miller. An efficient bit-level systolic cell design for finite ring digital signal processing applications
    209 -- 220Weijia Shang, José A. B. Fortes. On the optimality of linear schedules

    Volume 1, Issue 2

    91 -- 0Earl E. Swartzlander Jr.. Editorial
    93 -- 94José A. B. Fortes, S. Y. Kung. Introduction
    95 -- 113Patrice Quinton, Vincent Van Dongen. The mapping of linear recurrence equations on regular arrays
    115 -- 125Yoav Yaacoby, Peter R. Cappello. Scheduling a system of nonsingular affine recurrence equations onto a processor array
    127 -- 142Vwani P. Roychowdhury, Thomas Kailath. Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms
    143 -- 152Paul F. C. Krekel, Ed F. Deprettere. A systolic algorithm and architecture for solving sets of linear equations with multi-band coefficient matrix
    153 -- 162Fernando J. Nuñez, Mateo Valero. A block algorithm and optimal fixed-size systolic array processor for the algebraic path problem

    Volume 1, Issue 1

    5 -- 0Earl E. Swartzlander Jr.. Editorial
    9 -- 24S. C. Knowles, John G. McWhirter, Roger F. Woods, John V. McCanny. Bit-Level systolic architectures for high performance IIR filtering
    25 -- 34Takao Nishitani, Ichiro Tamitani, Hidenobu Harasaki, Yukio Endo, Toshiyuki Kanou, Koichi Kikuchi. Parallel video signal processor configuration based on overlap-save technique and its LSI processor element: VISP
    35 -- 43Nader Gharachorloo, Satish Gupta, Erdem Hokenek, Peruvemba Balasubramanian, William Bogholtz, Christian Mathieu, Christos Zoulas. A million transistor systolic array graphics engine
    45 -- 56K. Wojtek Przytula, J. Greg Nash. Parallel implementation of synthetic aperture radar algorithms
    57 -- 67Mitsuo Ishii, Hiroyuki Sato, Morio Ikesaka, Kouichi Murakami, Hiroaki Ishihata. Cellular array processor CAP and applications
    69 -- 84R. M. Lea. ASP modules: cost-effective building-blocks for real-time DSP systems
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